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公开(公告)号：US20250167695A1
公开(公告)日：2025-05-22
申请号：US18956211
申请日：2024-11-22
Applicant: NXP USA, Inc.
Inventor： Hans Halberstadt
Abstract: A controller for a resonant converter. If a measured current signal is greater than an upper-low-load-current-threshold, then the controller sets an upper-voltage-threshold-value based on the measured current signal. If the measured current signal is not greater than the upper-low-load-current-threshold, then the controller sets the upper-voltage-threshold-value based on the power setting signal but independent of the measured current signal. If the measured current signal is less than a lower-low-load-current-threshold, then the controller sets a lower-voltage-threshold-value based on the measured current signal. If the measured current signal is not less than the lower-low-load-current-threshold, then the controller sets the lower-voltage-threshold-value based on the power setting signal but independent of the measured current signal. In response to a measured voltage signal exceeding the upper-voltage-threshold-value, the controller opens the first switch and closes the second switch. In response to the measured voltage signal dropping below a lower-voltage-threshold-value, the controller opens the second switch and closes the first switch.
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公开(公告)号：US20250167677A1
公开(公告)日：2025-05-22
申请号：US18956137
申请日：2024-11-22
Applicant: NXP USA, Inc.
Inventor： Remco Twelkemeijer , Hans Halberstadt , Frank van Rens
Abstract: A controller for a resonant converter. The resonant converter comprising: a first switch and a second switch connected in series with each other between the supply source and a reference terminal; and a resonant tank that is electrically connected to the first and second switches, wherein the resonant tank comprises a resonant capacitor. The controller is configured to: receive a measured voltage signal that represents the voltage at a predetermined point in the resonant tank; determine voltage-correction-signalling based on a measured current signal, which represents the current flowing in the resonant tank; and in response to the measured voltage signal crossing a voltage threshold value, after the application of the voltage-correction-signalling to either the measured voltage signal or the voltage threshold value as an offset, change the state of the first switch and the second switch.
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公开(公告)号：US20250142923A1
公开(公告)日：2025-05-01
申请号：US18499088
申请日：2023-10-31
Applicant: NXP USA, Inc.
Inventor： Bernhard Grote , Bruce McRae Green
IPC: H01L29/40 , H01L29/417 , H01L29/66 , H01L29/778
Abstract: A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that is recessed below the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is higher than the first horizontal bottom extent of the first gate field plate.
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公开(公告)号：US20250142922A1
公开(公告)日：2025-05-01
申请号：US18499083
申请日：2023-10-31
Applicant: NXP USA, Inc.
Inventor： Bernhard Grote , Bruce McRae Green
IPC: H01L29/40 , H01L29/417 , H01L29/66 , H01L29/78
Abstract: A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate.
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公开(公告)号：US20250132709A1
公开(公告)日：2025-04-24
申请号：US18491896
申请日：2023-10-23
Applicant: NXP USA, INC.
Inventor： Jozef Janosik , Marek Stulrajter , Marek Musak
Abstract: Current sensing circuits for motor control applications are discussed. In some embodiments, a circuit may include a shunt resistor network coupled to an inverter having a plurality of phase legs, where each of the plurality of phase legs is configured to drive a respective phase of an electrical motor, and an Operational Amplifier (Op Amp) coupled across the shunt resistor network, where the Op Amp enables a processor to reconstruct electrical currents in each of the plurality of phase legs.
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Patent Agency Ranking
公开(公告)号：US20250126716A1
公开(公告)日：2025-04-17
申请号：US18486179
申请日：2023-10-13
Applicant: NXP USA, Inc.
Inventor： Boon Yew Low , Fui Yee Lim , Fernando A. Santos , Dominic (PohMeng) Koey
Abstract: A circuit module includes a module substrate with a mounting surface, and a plurality of conductive features and electronic circuitry coupled to the mounting surface. Encapsulant material covers the electronic circuitry and the mounting surface, and an upper surface of the encapsulant material defined a first surface of the circuit module. A plurality of leadframe terminals, each separated from a non-planar leadframe unit, extend from the conductive features at the mounting surface through the encapsulant material toward the first surface of the circuit module. Each of the leadframe terminals is formed from an elongated planar conductive feature of a leadframe unit, and the plurality of leadframe terminals is electrically coupled to the electronic circuitry through the conductive features and the module substrate. Encapsulant divots may extend into the encapsulant material from the first surface of the circuit module, and proximal ends of the leadframe terminals terminate at the encapsulant divots.
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公开(公告)号：US12278642B2
公开(公告)日：2025-04-15
申请号：US17992852
申请日：2022-11-22
Applicant: NXP USA, Inc.
Inventor： Ya-Wei Huang
Abstract: A time-synchronization apparatus and/or method involves identifying a frequency offset by implementing a frequency-offset-acquisition process which includes counting cycles of a local clock signal within a period of a reference pulse train. A phase offset of the local clock signal is determined, a residual frequency error is generated based on the phase offset, and at least one timer-adjustment signal that is based on the frequency offset and the residual frequency error is provided.
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公开(公告)号：US20250112627A1
公开(公告)日：2025-04-03
申请号：US18891369
申请日：2024-09-20
Applicant: NXP USA, Inc.
Abstract: In a system on a chip (SoC), clock selection circuitry provides a selected one of a first or second clock signal as an output clock based on at least one of a first flag and a second flag. This output clock is provided as a reference clock to one or more phase locked loops (PLLs) of the SoC. The SoC includes a first clock path which receives a first oscillating signal from a first clock source external to the SoC to generate the first clock signal, and a second clock path which receives a second oscillating signal from a second clock source external to the SoC to generate the second clock signal. A first glitch monitor asserts the first flag when a glitch is detected in the first oscillating signal, and a second glitch monitor configured asserts the second flag when a glitch is detected in the second oscillating signal.
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公开(公告)号：US12267082B2
公开(公告)日：2025-04-01
申请号：US18459289
申请日：2023-08-31
Applicant: NXP USA, Inc.
Inventor： Pragya Priya Malakar , John Pigott
Abstract: Oscillator circuitry and methods of operation thereof are provided in which the oscillator circuitry includes at least a first oscillator, a second oscillator, and a lock detector. The first oscillator is configured to generate a first clock signal. The second oscillator is configured to generate a second clock signal. The lock detector is configured to detect a stable phase lock between the first clock signal and the second clock signal and to switch an output of the oscillator circuitry from the first clock signal to the second clock signal in response to detecting the stable phase lock.
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公开(公告)号：US20250106152A1
公开(公告)日：2025-03-27
申请号：US18889810
申请日：2024-09-19
Applicant: NXP USA, Inc.
Inventor： David McDaid , Jeffrey Thomas Loeliger
IPC: H04L45/74 , H04L45/302
Abstract: A communication interface includes a first and second interface module to provide for point-to-point transmission of signalling to a second or third node respectively and receipt of signalling from the second node or third node respectively via one or more first terminals. The first and second interface modules include one or more second terminals to communicatively couple a first processor and the first or second interface module. At least one interface-to-interface connection couples the first interface module and the second interface module. A routing module reads a data frame and, based on whether or not an identifier present in a routing field of the data frame matches one or more predetermined identifiers, provides for forwarding of the data frame to the first processor or to the interface-to-interface connection for retransmission by the other of the first interface module and the second interface module.
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