公开(公告)号：US08847431B2

公开(公告)日：2014-09-30

申请号：US13289599

申请日：2011-11-04

申请人： Taihei Shido ,  Mototsugu Fujimitsu ,  Nobuhiro Oodaira ,  Naoki Kitai

发明人： Taihei Shido ,  Mototsugu Fujimitsu ,  Nobuhiro Oodaira ,  Naoki Kitai

IPC分类号： H04B3/00

CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first circuit, a second circuit, a first wire, and a pair of shield lines. The first circuit includes a voltage generating circuit generating a predetermined voltage and produces the predetermined voltage at an output end thereof. The first wire connects the output end of the first circuit to an input end of the second circuit. The pair of shield lines is disposed so as to sandwich the first wire therebetween. One of the shield lines is supplied with a power supply potential for driving at least one of the voltage generating circuit and the second circuit. Another of the shield lines is supplied with a ground potential for driving at least one of the voltage generating circuit and the second circuit.

摘要翻译： 半导体器件包括第一电路，第二电路，第一线和一对屏蔽线。 第一电路包括产生预定电压并在其输出端产生预定电压的电压产生电路。 第一线将第一电路的输出端连接到第二电路的输入端。 一对屏蔽线设置成将第一线夹在其间。 一个屏蔽线被提供有用于驱动电压产生电路和第二电路中的至少一个的电源电位。 另一个屏蔽线被提供有用于驱动电压产生电路和第二电路中的至少一个的接地电位。

公开(公告)号：US08437179B2

公开(公告)日：2013-05-07

申请号：US13528025

申请日：2012-06-20

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US20120112563A1

公开(公告)日：2012-05-10

申请号：US13289599

申请日：2011-11-04

申请人： Taihei SHIDO ,  Mototsugu FUJIMITSU ,  Nobuhiro OODAIRA ,  Naoki KITAI

发明人： Taihei SHIDO ,  Mototsugu FUJIMITSU ,  Nobuhiro OODAIRA ,  Naoki KITAI

IPC分类号： H01B7/30

CPC分类号： H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first circuit, a second circuit, a first wire, and a pair of shield lines. The first circuit includes a voltage generating circuit generating a predetermined voltage and produces the predetermined voltage at an output end thereof. The first wire connects the output end of the first circuit to an input end of the second circuit. The pair of shield lines is disposed so as to sandwich the first wire therebetween. One of the shield lines is supplied with a power supply potential for driving at least one of the voltage generating circuit and the second circuit. Another of the shield lines is supplied with a ground potential for driving at least one of the voltage generating circuit and the second circuit.

摘要翻译： 半导体器件包括第一电路，第二电路，第一线和一对屏蔽线。 第一电路包括产生预定电压并在其输出端产生预定电压的电压产生电路。 第一线将第一电路的输出端连接到第二电路的输入端。 一对屏蔽线设置成将第一线夹在其间。 一个屏蔽线被提供有用于驱动电压产生电路和第二电路中的至少一个的电源电位。 另一个屏蔽线被提供有用于驱动电压产生电路和第二电路中的至少一个的接地电位。

公开(公告)号：US20110215414A1

公开(公告)日：2011-09-08

申请号：US13067177

申请日：2011-05-13

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/092

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US07964484B2

公开(公告)日：2011-06-21

申请号：US12457917

申请日：2009-06-25

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L21/425 ,  H01L29/167

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20110128780A1

公开(公告)日：2011-06-02

申请号：US13024252

申请日：2011-02-09

申请人： Kenichi OSADA ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

发明人： Kenichi OSADA ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092 ,  G11C2213/79

摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.

摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。

公开(公告)号：US07907435B2

公开(公告)日：2011-03-15

申请号：US11915126

申请日：2005-09-21

申请人： Kenichi Osada ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

发明人： Kenichi Osada ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092 ,  G11C2213/79

摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.

公开(公告)号：US20090073753A1

公开(公告)日：2009-03-19

申请号：US11915126

申请日：2005-09-21

申请人： Kenichi Osada ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

发明人： Kenichi Osada ,  Naoki Kitai ,  Takayuki Kawahara ,  Kazumasa Yanagisawa

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0092 ,  G11C2213/79

摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.

摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。

公开(公告)号：US20080203437A1

公开(公告)日：2008-08-28

申请号：US12078992

申请日：2008-04-09

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/11 ,  G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US07388238B2

公开(公告)日：2008-06-17

申请号：US11452275

申请日：2006-06-14

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/10

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.