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公开(公告)号：US20160004458A1
公开(公告)日：2016-01-07
申请号：US14325212
申请日：2014-07-07
申请人： PMC-SIERRA US, INC.
发明人： Rino Micheloni , Alessia Marelli , Luca Crippa
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/00
摘要： A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools.
摘要翻译： 用于非易失性存储器件中的存储块池擦除均衡的系统和方法。 通过识别非易失性存储器系统的多个存储器块池来识别非易失性存储器系统的改进的误码率，识别多个存储器块池中的每一个的松弛时间延迟并执行预定数量的编程/擦除周期 基于所述存储器块池的所述弛豫时间延迟，针对所述多个存储器块池中的每一个。
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2.发明申请公开(公告)号：US20140281828A1
公开(公告)日：2014-09-18
申请号：US14210971
申请日：2014-03-14
申请人： PMC-SIERRA US, INC.
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie , Ihab Jaser , Luca Crippa
IPC分类号： H03M13/11
CPC分类号： G06F11/00 , G06F11/1048 , H03M13/1111 , H03M13/3769
摘要： A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.
摘要翻译： 读取，累加和处理用于LDPC解码的软信息的系统和方法。 根据本发明，LDPC解码器包括用于接收非易失性存储器存储模块的单元的软读取的积累电路，并且产生可用于识别该单元的适当LLR的累积软读。 本发明的累积电路可以包括累加RAM，算术逻辑单元（ALU）和用于累积和处理用于LDPC解码的软信息的软累积控制和排序模块。
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公开(公告)号：US08990661B1
公开(公告)日：2015-03-24
申请号：US13785848
申请日：2013-03-05
申请人： PMC-Sierra US, Inc.
CPC分类号： H03M13/114 , G06F11/1048 , H03M13/112
摘要： A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein a layer specific attenuation factor is provided for each layer of the LDPC parity check matrix. An attenuation factor matrix comprising a plurality of coefficients specifies the specific attenuation factor for each layer and each iteration of the decoding process. A check node processor performs check node processing for each layer of the parity check matrix associated with the LDPC encoded codeword utilizing the normalized layered min-sum algorithm wherein the attenuation factor of the min-sum algorithm is determined by the coefficients of the attenuation factor matrix.
摘要翻译： 提供了一种用于解码低密度奇偶校验（LDPC）编码数据的低密度奇偶校验（LDPC）解码器，其中为LDPC奇偶校验矩阵的每一层提供层特定衰减因子。 包括多个系数的衰减因子矩阵指定每个层的特定衰减因子和解码过程的每次迭代。 校验节点处理器利用归一化分层最小和算法对与LDPC编码码字相关联的奇偶校验矩阵的每一层执行校验节点处理，其中最小和算法的衰减因子由衰减因子矩阵的系数确定 。
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4.发明申请SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSITY PARITY CHECK DECODING 有权具有低密度奇偶校验解码的参考电压分配的系统和方法公开(公告)号：US20140281823A1
公开(公告)日：2014-09-18
申请号：US14165135
申请日：2014-01-27
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/1012 , H03M13/1111 , H03M13/3723
摘要： A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.
摘要翻译： 一种用于将对数似然比（LLR）提供给低密度奇偶校验（LDPC）解码器的非易失性存储器控制器，用于对LDPC编码码字的解码。 控制器包括分配电路，用于基于非易失性存储器的估计的BER识别具有最小计算的引入的误差值的一组软判决参考电压。 控制器还包括读取电路，用于使用具有最小计算的LLR引入的误差值的软判决参考电压集来读取存储在非易失性存储器存储模块中的LDPC编码码字，以提供表示代码字的多个软判决位。 所述控制器还包括可由读取电路访问的LLR查找表，以向所述LDPC解码器提供LLR用于所述码字的后续解码。
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5.发明申请SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING 有权用于LDPC解码中的高质量日志比特率的系统和方法公开(公告)号：US20140281800A1
公开(公告)日：2014-09-18
申请号：US14210067
申请日：2014-03-13
申请人： PMC-SIERRA US, INC.
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie , Ihab Jaser , Luca Crippa
IPC分类号： H03M13/11
CPC分类号： H03M13/1111 , G06F11/10 , G06F11/1012 , H03M13/15 , H03M13/255 , H03M13/3723 , H03M13/3927 , H04L1/0057
摘要： A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.
摘要翻译： 提供了一种非易失性存储器存储控制器，用于将对数似然比（LLR）传送到用于LDPC编码码字的解码中的低密度奇偶校验（LDPC）解码器。 控制器包括用于使用多个软判决参考电压读取存储在非易失性存储器存储模块中的LDPC编码码字的读取电路，以提供表示代码字的多个软判决位。 控制器还包括表示相邻小区对存储器存储模块的阈值电压分布的贡献的多个相邻小区贡献LLR查找表。 控制器将来自适当的LLR查找表的LLR提供给用于码字的后续解码的LDPC解码器。
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6.发明授权System and method with reference voltage partitioning for low density parity check decoding 有权具有参考电压分配的系统和方法，用于低密度奇偶校验解码公开(公告)号：US09235467B2
公开(公告)日：2016-01-12
申请号：US14165135
申请日：2014-01-27
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/1012 , H03M13/1111 , H03M13/3723
摘要： A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.
摘要翻译： 一种用于将对数似然比（LLR）提供给低密度奇偶校验（LDPC）解码器的非易失性存储器控制器，用于对LDPC编码码字的解码。 控制器包括分配电路，用于基于非易失性存储器的估计的BER识别具有最小计算的引入的误差值的一组软判决参考电压。 控制器还包括读取电路，用于使用具有最小计算的LLR引入的误差值的软判决参考电压集来读取存储在非易失性存储器存储模块中的LDPC编码码字，以提供表示代码字的多个软判决位。 所述控制器还包括可由读取电路访问的LLR查找表，以向所述LDPC解码器提供LLR用于所述码字的后续解码。
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7.发明授权Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system 有权基于LDPC码的装置和方法，用于调整存储器系统中可校正的原始误码率限制公开(公告)号：US09092353B1
公开(公告)日：2015-07-28
申请号：US13752885
申请日：2013-01-29
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/1068 , G06F11/1008 , G11C29/52 , H03M13/11 , H03M13/1108 , H03M13/1111 , H03M13/116 , H03M13/2957 , H03M13/3715 , H03M13/45
摘要： Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.
摘要翻译： 用于校正从存储器单元读取的数据中的错误的系统和方法包括存储器控制器，其包括编码器和解码器。 存储器控制器被配置为调整可校正的原始误码率限制，以校正从存储器单元读取的数据中发生的不同位错误率。 通过切换硬判决解码和软判决解码之间的解码来调整可校正的原始误码率限制，其中在软判决解码期间可以改变分配给消息值的软比特数。 通过在对同一编码器和解码器进行虚拟调整的同时改变存储器系统内的码率来调整可校正的原始误码率。
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8.发明授权公开(公告)号：US09305661B2
公开(公告)日：2016-04-05
申请号：US14475757
申请日：2014-09-03
申请人： PMC-SIERRA US, INC.
发明人： Rino Micheloni , Luca Crippa
CPC分类号： G11C16/349 , G11C16/10 , G11C16/32 , G11C16/3427
摘要： A nonvolatile memory system and a method for using programming time to reduce bit errors in the nonvolatile memory system are disclosed. The method includes programming a plurality of memory cells of a nonvolatile memory device, identifying weak cells using programming time and preventing subsequent programming to the identified weak cells.
摘要翻译： 公开了一种非易失性存储器系统和用于使用编程时间来减少非易失性存储器系统中的位错误的方法。 该方法包括对非易失性存储器件的多个存储器单元进行编程，使用编程时间识别弱单元，并防止对所识别的弱单元的后续编程。
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9.发明申请公开(公告)号：US20160064096A1
公开(公告)日：2016-03-03
申请号：US14475757
申请日：2014-09-03
申请人： PMC-SIERRA US, INC.
发明人： Rino Micheloni , Luca Crippa
CPC分类号： G11C16/349 , G11C16/10 , G11C16/32 , G11C16/3427
摘要： A nonvolatile memory system and a method for using programming time to reduce bit errors in the nonvolatile memory system are disclosed. The method includes programming a plurality of memory cells of a nonvolatile memory device, identifying weak cells using programming time and preventing subsequent programming to the identified weak cells.
摘要翻译： 公开了一种非易失性存储器系统和用于使用编程时间来减少非易失性存储器系统中的位错误的方法。 该方法包括对非易失性存储器件的多个存储器单元进行编程，使用编程时间识别弱单元，并防止对所识别的弱单元的后续编程。
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10.发明授权Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values 有权在使用强对数似然（LLR）值的存储器系统中调整可校正原始误码率限制的装置和方法公开(公告)号：US09128858B1
公开(公告)日：2015-09-08
申请号：US13752757
申请日：2013-01-29
申请人： PMC-SIERRA US, INC.
CPC分类号： G06F11/10 , G06F11/1048 , H03M13/09 , H03M13/1102 , H03M13/116 , H03M13/1194 , H03M13/1197 , H03M13/152 , H03M13/29 , H03M13/353 , H03M13/3707 , H03M13/3738 , H03M13/618
摘要： Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.
摘要翻译： 用于校正从集成电路装置的存储器单元读取的数据中的错误的装置和方法包括编码器。 编码器由单个奇偶校验矩阵配置，并且编码器被配置为通过将编码器中的位数设置为零而实际上可调节。 解码器由单个奇偶校验矩阵配置，并且解码器被配置为通过将解码器中的位数的对数似然比（LLR）设置为强值来实际可调节。 编码器和解码器使用的码率可以通过调整编码器中设置为零的位数和解码器中被设置为强LLR值的位数来改变。
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