Method for culturing stem cells
    1.
    发明授权
    Method for culturing stem cells 有权
    培养干细胞的方法

    公开(公告)号:US09163214B2

    公开(公告)日:2015-10-20

    申请号:US13379651

    申请日:2010-05-04

    摘要: In the field of biological technology, a stem cell culture method is provided. The method includes preparing an amniotic epithelial cell feeder layer that is not treated to lose the division ability; and seeding the stem cells onto the amniotic epithelial cell feeder layer, and culturing in a culture medium. The stem cell culture method according to the present invention does not require the treatment of the feeder layer cells to lose the division ability, and is thus simple and safe, thereby effectively solving the problem of contamination caused by animal-derived ingredients in culture of human stem cells at present, greatly reducing the culture cost of the stem cells, and providing a safe, effective, and inexpensive stem cell culture method for the industrialization of the stem cells in the future.

    摘要翻译: 在生物技术领域,提供了干细胞培养方法。 该方法包括制备未被处理以丧失分裂能力的羊膜上皮细胞饲养层; 并将干细胞接种到羊膜上皮细胞饲养层上,并在培养基中培养。 根据本发明的干细胞培养方法不需要对饲养层细胞的处理以失去分裂能力,因此简单安全,从而有效地解决了动物来源的成分在人类培养中引起的污染问题 目前干细胞大大降低了干细胞的培养成本,为将来干细胞工业化提供了一种安全,有效,廉价的干细胞培养方法。

    Structures for power transistor and methods of manufacture
    2.
    发明授权
    Structures for power transistor and methods of manufacture 有权
    功率晶体管和制造方法的结构

    公开(公告)号:US08823098B2

    公开(公告)日:2014-09-02

    申请号:US13414292

    申请日:2012-03-07

    申请人: Qin Huang Yuming Bai

    发明人: Qin Huang Yuming Bai

    摘要: The invention discloses a manufacture method and structure of a power transistor, comprising a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode. The two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the two gate units; the upper electrode covers the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.

    摘要翻译: 本发明公开了一种功率晶体管的制造方法和结构,包括下电极,衬底,漂移区,两个第一导电区,两个第二导电区,两个栅极单元,隔离结构和上电极。 两个第二导电区域在两个第一导电区域和漂移区域之间; 两个栅极单元在两个第二导电区域上; 隔离结构覆盖两个门单元; 上电极覆盖隔离结构并且电连接到两个第一导电区域和两个第二导电区域。 当衬底是第一导电类型时,该结构可以用作MOSFET。 当基板是第二导电类型时,该结构可以用作IGBT。 该结构具有较小的栅电极面积,导致Qg,Qgd和Rdson较少,提高器件性能。

    VERTICAL COMPLEMENTARY FET
    3.
    发明申请
    VERTICAL COMPLEMENTARY FET 失效
    垂直补充FET

    公开(公告)号:US20120228698A1

    公开(公告)日:2012-09-13

    申请号:US13413175

    申请日:2012-03-06

    申请人: Qin HUANG

    发明人: Qin HUANG

    IPC分类号: H01L27/092

    摘要: A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit. A part of the substrate bottom of the invention extends into the middle layer and form the plug between the two MOS units. There is an output terminal under the substrate layer. When on-state voltage is applied on the gate electrode of the two MOS units, two conduction paths are formed from MOS unit-plug-substrate to the output terminal. This technology can integrate more than two MOS devices. Therefore, the die size is reduced.

    摘要翻译: 垂直互补场效应晶体管(FET)涉及半导体芯片的生产技术,更具体地涉及功率集成电路的生产技术。 本发明的基板底部的一部分延伸到中间层,并在两个MOS单元之间形成插头。 在基底层下面有一个输出端子。 当在两个MOS单元的栅电极上施加通态电压时,从MOS单元插头基板到输出端子形成两个导通路径。 该技术可以集成两个以上的MOS器件。 因此,管芯尺寸减小。

    Solid-state DC circuit breaker
    5.
    发明授权
    Solid-state DC circuit breaker 失效
    固态直流断路器

    公开(公告)号:US06952335B2

    公开(公告)日:2005-10-04

    申请号:US10390712

    申请日:2003-03-19

    CPC分类号: H02H3/087 H03K17/08148

    摘要: A high-speed, solid-state circuit breaker is capable of interrupting high DC currents without generating an arc, and it is maintenance-free. Both the switch and the tripping unit are solid-state, which meet precise protection requirements. The high-speed, solid-state DC circuit breaker uses an emitter turn-off (ETO) thyristor as the switch. The ETO thyristor has an anode, a cathode and first, second and third gate electrodes. The anode is connectable to a source of DC current, and the cathode is connectable to a load. A solid-state trip circuit is connected to the first, second and third gate electrodes for controlling interrpution of DC current to the load by turning off said ETO thyristor.

    摘要翻译: 高速固态断路器能够在不产生电弧的情况下中断高直流电流,而且无需维护。 开关和脱扣单元均为固态,符合精确的保护要求。 高速固态直流断路器使用发射极关断(ETO)晶闸管作为开关。 ETO晶闸管具有阳极,阴极和第一,第二和第三栅电极。 阳极可连接到直流电源,阴极可连接到负载。 固态跳闸电路连接到第一,第二和第三栅电极,用于通过关断所述ETO晶闸管来控制到负载的直流电流的间断。

    Trench contact process
    6.
    发明授权
    Trench contact process 失效
    沟槽接触过程

    公开(公告)号:US6110799A

    公开(公告)日:2000-08-29

    申请号:US885879

    申请日:1997-06-30

    申请人: Qin Huang

    发明人: Qin Huang

    摘要: A trench process for establishing a contact for a semiconductor device with trenches such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs which reduces the number of masks and eliminates the need for lateral diffusion into the trench channel region. Improved control of the parasitic transistor in the trench MOSFET is also achieved. The cell size/pitch is reduced relative to conventional processes which require source block and P+ masks.

    摘要翻译: 用于建立具有诸如沟槽和平面MOSFET(UOS),沟槽和平面IGBT以及沟槽MCT的沟槽的半导体器件的接触的沟槽工艺,其减少了掩模的数量并且消除了对沟槽沟道区域的横向扩散的需要。 还实现了沟槽MOSFET中寄生晶体管的改进控制。 相对于需要源块和P +掩模的常规工艺,单元尺寸/间距减小。

    Intelligent integrated battery module
    7.
    发明授权
    Intelligent integrated battery module 有权
    智能集成电池模块

    公开(公告)号:US09444275B2

    公开(公告)日:2016-09-13

    申请号:US13600280

    申请日:2012-08-31

    申请人: Qin Huang Yu Du

    发明人: Qin Huang Yu Du

    摘要: An energy storage system is provided. The system includes a plurality of energy storage modules connected in parallel. Each energy storage module has an energy storage source, a bidirectional current converter configured for supplying charge to the energy storage source from a power source and for discharging current for use by an electrical device, a monitoring module for monitoring the energy storage source and the current converter, and a controller configured to control the current converter based upon monitored characteristics of the storage source and the current converter to produce a respective output signal for each module. A communications module is in connection with each output signal of the energy storage modules and configured for communicating a combined output signal with one of the power source and the electrical device.

    摘要翻译: 提供储能系统。 该系统包括并联连接的多个能量存储模块。 每个能量存储模块具有能量存储源,双向电流转换器,其被配置为从电源向能量存储源提供电荷并且用于放电以供电子设备使用;监视模块,用于监视能量存储源和电流 转换器和配置成基于所监视的存储源和电流转换器的特性来控制电流转换器以产生每个模块的相应输出信号的控制器。 通信模块与能量存储模块的每个输出信号相连,并被配置为将组合的输出信号与电源和电气设备之一进行通信。

    Vertical complementary FET
    8.
    发明授权
    Vertical complementary FET 失效
    垂直互补FET

    公开(公告)号:US08476710B2

    公开(公告)日:2013-07-02

    申请号:US13413175

    申请日:2012-03-06

    申请人: Qin Huang

    发明人: Qin Huang

    IPC分类号: H01L23/62

    摘要: A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit. A part of the substrate bottom of the invention extends into the middle layer and form the plug between the two MOS units. There is an output terminal under the substrate layer. When on-state voltage is applied on the gate electrode of the two MOS units, two conduction paths are formed from MOS unit-plug-substrate to the output terminal. This technology can integrate more than two MOS devices. Therefore, the die size is reduced.

    摘要翻译: 垂直互补场效应晶体管(FET)涉及半导体芯片的生产技术,更具体地涉及功率集成电路的生产技术。 本发明的基板底部的一部分延伸到中间层,并在两个MOS单元之间形成插头。 在基底层下面有一个输出端子。 当在两个MOS单元的栅电极上施加通态电压时,从MOS单元插头基板到输出端子形成两个导通路径。 该技术可以集成两个以上的MOS器件。 因此,管芯尺寸减小。

    ISOLATED SOFT-SWITCH SINGLE-STAGE AC-DC CONVERTER
    9.
    发明申请
    ISOLATED SOFT-SWITCH SINGLE-STAGE AC-DC CONVERTER 有权
    隔离式软开关单级AC-DC转换器

    公开(公告)号:US20130051102A1

    公开(公告)日:2013-02-28

    申请号:US13595883

    申请日:2012-08-27

    IPC分类号: H02M7/04 H02M7/155 H02M7/217

    CPC分类号: H02M7/217

    摘要: An alternating current-to-direct current (AC-DC) converter is provided. The converter may include a transformer having a primary side and a secondary side. A first bi-directional switch and a first inductor may be connected in series between a positive terminal of an AC source and a first terminal of the primary side of the transformer. A second bi-directional switch and a second inductor may be connected between the positive terminal of the AC source and a second terminal of the primary side of the transformer and connected in parallel with the first bi-directional switch.

    摘要翻译: 提供交流电直流电(AC-DC)转换器。 转换器可以包括具有初级侧和次级侧的变压器。 第一双向开关和第一电感器可以串联连接在AC电源的正极端子和变压器初级侧的第一端子之间。 第二双向开关和第二电感器可以连接在AC源的正极端子和变压器初级侧的第二端子之间并与第一双向开关并联连接。

    Trench emitter controlled thyristor
    10.
    发明授权
    Trench emitter controlled thyristor 失效
    沟槽发射极控制晶闸管

    公开(公告)号:US5998811A

    公开(公告)日:1999-12-07

    申请号:US24117

    申请日:1998-02-17

    申请人: Qin Huang

    发明人: Qin Huang

    IPC分类号: H01L29/745 H01L29/749

    CPC分类号: H01L29/7455 H01L29/749

    摘要: A trench emitter controlled thyristor 30 having a collector layer 32, a drift layer 34, a body layer 36, and a floating layer 38. Each of the layers 32, 34, 36, and 38 contacts the adjacent layer(s). The floating layer 38 does not cover the entirety of the adjacent layer (the body layer 36) but at one of the lateral ends of the thyristor 30, an emitter 40 is formed. A gate area (or electrode) 43 is formed to span laterally across the thyristor 30. Additionally, trenches are formed into the lateral edges 44 of the body layer 36 and a portion of the drift layer 34. Within the trenches 44 are formed additional gate area 42 which runs for substantially the length of the thyristor 30. The gate 42 is kept electrically isolated from the remainder of the thyristor by an insulating region 46 directly over the body layer 36.

    摘要翻译: 具有集电极层32,漂移层34,主体层36和浮动层38的沟槽发射极控制晶闸管30。层32,34,36和38中的每一个接触相邻层。 浮动层38不覆盖相邻层(体层36)的整体,但是在晶闸管30的一个横向端部形成有发射体40。 形成栅极区域(或电极)43横跨晶闸管30跨越。此外,沟槽形成为主体层36的侧边缘44和漂移层34的一部分。在沟槽44内形成附加栅极 区域42的长度大致为晶闸管30的长度。门42通过直接在主体层36上方的绝缘区域46与晶闸管的其余部分保持电隔离。