公开(公告)号：US08823098B2

公开(公告)日：2014-09-02

申请号：US13414292

申请日：2012-03-07

申请人： Qin Huang ,  Yuming Bai

发明人： Qin Huang ,  Yuming Bai

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/788 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/7802 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/7396

摘要： The invention discloses a manufacture method and structure of a power transistor, comprising a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode. The two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the two gate units; the upper electrode covers the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.

摘要翻译： 本发明公开了一种功率晶体管的制造方法和结构，包括下电极，衬底，漂移区，两个第一导电区，两个第二导电区，两个栅极单元，隔离结构和上电极。 两个第二导电区域在两个第一导电区域和漂移区域之间; 两个栅极单元在两个第二导电区域上; 隔离结构覆盖两个门单元; 上电极覆盖隔离结构并且电连接到两个第一导电区域和两个第二导电区域。 当衬底是第一导电类型时，该结构可以用作MOSFET。 当基板是第二导电类型时，该结构可以用作IGBT。 该结构具有较小的栅电极面积，导致Qg，Qgd和Rdson较少，提高器件性能。

公开(公告)号：US08604541B2

公开(公告)日：2013-12-10

申请号：US13441101

申请日：2012-04-06

申请人： Qin Huang ,  Yuming Bai ,  Yang Gao

发明人： Qin Huang ,  Yuming Bai ,  Yang Gao

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7396

摘要： This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.

摘要翻译： 本发明公开了一种具体的超结MOSFET结构及其制造工艺。 这种结构包括：漏极，衬底，EPI，源极，侧壁隔离结构，栅极，栅极隔离层和源极。 在源下面的活动区域内有隔离层。 沿着该隔离层的侧壁，可以引入与主体相同的掺杂类型的缓冲层，并且还可以将源延伸以形成场板。 这种缓冲层和场板可以使EPI掺杂比常规器件高得多，这导致较低的Rdson，更好的性能，更短的栅极，从而减小栅极电荷Qg和栅极至漏极电荷Qgd。 制造这种结构的过程更简单，更具成本效益。

公开(公告)号：US20070024251A1

公开(公告)日：2007-02-01

申请号：US11242915

申请日：2005-10-05

申请人： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

发明人： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

IPC分类号： G05F1/00

CPC分类号： G05F1/70

摘要： The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).

摘要翻译： 具有本发明的平均电流控制模式的连续导通模式（CCM）升压电压功率因数校正装置使用可复位积分器来积分从电压误差放大器输出的差分电压信号和从检测获得的输入电流信号。 然后将积分结果进行比较，以控制开关的占空比。 因此，AC / DC电力转换器的输入电流和输入电压具有比例关系，它们的相位彼此相同。 在该控制方法中使用的部件比现有技术的PFC电路简单。 在一个芯片中集成更少的引脚很容易。 本发明的装置具有高功率因数和低总谐波失真（THD）。

公开(公告)号：US06630711B2

公开(公告)日：2003-10-07

申请号：US10187560

申请日：2002-07-02

申请人： Qin Huang

发明人： Qin Huang

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/41716 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813

摘要： Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

公开(公告)号：US06437399B1

公开(公告)日：2002-08-20

申请号：US09498476

申请日：2000-02-04

申请人： Qin Huang

发明人： Qin Huang

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/41716 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813

摘要： Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

摘要翻译： 半导体结构如沟槽和平面MOSFET（UMOS），沟槽和平面IGBT以及使用沟槽建立导体的沟道MCT。 还实现了对沟槽MOSFET中的寄生晶体管的改进的控制，并且相对于传统结构，单元尺寸和间距减小。

公开(公告)号：US6037628A

公开(公告)日：2000-03-14

申请号：US885922

申请日：1997-06-30

申请人： Qin Huang

发明人： Qin Huang

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7813 ,  H01L29/41716 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/41766

摘要： Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

公开(公告)号：US09163214B2

公开(公告)日：2015-10-20

申请号：US13379651

申请日：2010-05-04

申请人： Dongmei Lai ,  Weiwei Cheng ,  Lihe Guo ,  Tianjin Liu ,  Lizhen Jiang ,  Qin Huang

发明人： Dongmei Lai ,  Weiwei Cheng ,  Lihe Guo ,  Tianjin Liu ,  Lizhen Jiang ,  Qin Huang

IPC分类号： C12N5/0735 ,  C12N5/074 ,  C12N5/095

CPC分类号： C12N5/0606 ,  C12N5/0607 ,  C12N2501/115 ,  C12N2501/235 ,  C12N2502/025

摘要： In the field of biological technology, a stem cell culture method is provided. The method includes preparing an amniotic epithelial cell feeder layer that is not treated to lose the division ability; and seeding the stem cells onto the amniotic epithelial cell feeder layer, and culturing in a culture medium. The stem cell culture method according to the present invention does not require the treatment of the feeder layer cells to lose the division ability, and is thus simple and safe, thereby effectively solving the problem of contamination caused by animal-derived ingredients in culture of human stem cells at present, greatly reducing the culture cost of the stem cells, and providing a safe, effective, and inexpensive stem cell culture method for the industrialization of the stem cells in the future.

摘要翻译： 在生物技术领域，提供了干细胞培养方法。 该方法包括制备未被处理以丧失分裂能力的羊膜上皮细胞饲养层; 并将干细胞接种到羊膜上皮细胞饲养层上，并在培养基中培养。 根据本发明的干细胞培养方法不需要对饲养层细胞的处理以失去分裂能力，因此简单安全，从而有效地解决了动物来源的成分在人类培养中引起的污染问题 目前干细胞大大降低了干细胞的培养成本，为将来干细胞工业化提供了一种安全，有效，廉价的干细胞培养方法。

公开(公告)号：US07256569B2

公开(公告)日：2007-08-14

申请号：US11242915

申请日：2005-10-05

申请人： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

发明人： Chung-Cheng Wu ,  Qin Huang ,  Ning Zhu ,  Xin Zhang

IPC分类号： G05F1/10 ,  G05F1/40 ,  H02H7/00

CPC分类号： G05F1/70

摘要： The continuous conduction mode (CCM) boost voltage power factor correction apparatus with an average-current control mode of the present invention uses resettable integrators to integrate the difference voltage signal outputted from the voltage error amplifier and the input current signal obtained from detection. The integration results are then compared to control the duty cycle of the switch. Thereby, the input current and the input voltage in the AC/DC electrical power converter have a proportion relation and their phases are the same as each other. The components used in this control method are simpler than the PFC circuit of the prior art. It is easy to integrate in one chip with fewer pins. The apparatus of the present invention has a high power factor and a low total harmonic distortion (THD).

公开(公告)号：US06952335B2

公开(公告)日：2005-10-04

申请号：US10390712

申请日：2003-03-19

申请人： Qin Huang ,  Xigen Zhou ,  Zhenxue Xu

发明人： Qin Huang ,  Xigen Zhou ,  Zhenxue Xu

IPC分类号： H02H3/087 ,  H03K17/0814 ,  H02H3/00

CPC分类号： H02H3/087 ,  H03K17/08148

摘要： A high-speed, solid-state circuit breaker is capable of interrupting high DC currents without generating an arc, and it is maintenance-free. Both the switch and the tripping unit are solid-state, which meet precise protection requirements. The high-speed, solid-state DC circuit breaker uses an emitter turn-off (ETO) thyristor as the switch. The ETO thyristor has an anode, a cathode and first, second and third gate electrodes. The anode is connectable to a source of DC current, and the cathode is connectable to a load. A solid-state trip circuit is connected to the first, second and third gate electrodes for controlling interrpution of DC current to the load by turning off said ETO thyristor.

摘要翻译： 高速固态断路器能够在不产生电弧的情况下中断高直流电流，而且无需维护。 开关和脱扣单元均为固态，符合精确的保护要求。 高速固态直流断路器使用发射极关断（ETO）晶闸管作为开关。 ETO晶闸管具有阳极，阴极和第一，第二和第三栅电极。 阳极可连接到直流电源，阴极可连接到负载。 固态跳闸电路连接到第一，第二和第三栅电极，用于通过关断所述ETO晶闸管来控制到负载的直流电流的间断。

公开(公告)号：US6110799A

公开(公告)日：2000-08-29

申请号：US885879

申请日：1997-06-30

申请人： Qin Huang

发明人： Qin Huang

IPC分类号： H01L29/74 ,  H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/1095 ,  H01L29/41766

摘要： A trench process for establishing a contact for a semiconductor device with trenches such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs which reduces the number of masks and eliminates the need for lateral diffusion into the trench channel region. Improved control of the parasitic transistor in the trench MOSFET is also achieved. The cell size/pitch is reduced relative to conventional processes which require source block and P+ masks.

摘要翻译： 用于建立具有诸如沟槽和平面MOSFET（UOS），沟槽和平面IGBT以及沟槽MCT的沟槽的半导体器件的接触的沟槽工艺，其减少了掩模的数量并且消除了对沟槽沟道区域的横向扩散的需要。 还实现了沟槽MOSFET中寄生晶体管的改进控制。 相对于需要源块和P +掩模的常规工艺，单元尺寸/间距减小。