公开(公告)号：US20150052333A1

公开(公告)日：2015-02-19

申请号：US14341643

申请日：2014-07-25

申请人： Christopher J. HUGHES ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Bret TOLL ,  Robert C. VALENTINE ,  Milind B. GIRKAR ,  Andrew T. FORSYTH ,  Edward T. GROCHOWSKI ,  Jonathan C. HALL

发明人： Christopher J. HUGHES ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Bret TOLL ,  Robert C. VALENTINE ,  Milind B. GIRKAR ,  Andrew T. FORSYTH ,  Edward T. GROCHOWSKI ,  Jonathan C. HALL

IPC分类号： G06F9/30

摘要： Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask.

摘要翻译： 描述了用于在计算机处理器中执行收集和散播步幅指令的系统，装置和方法的实施例。 在一些实施例中，根据写入掩码的位值的至少一些，执行收集步幅指令导致从存储器进入到目的地寄存器的条带数据元素的有条件存储。

公开(公告)号：US06073213A

公开(公告)日：2000-06-06

申请号：US982097

申请日：1997-12-01

申请人： Guy Peled ,  Robert C. Valentine ,  Oded Lempel

发明人： Guy Peled ,  Robert C. Valentine ,  Oded Lempel

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3808 ,  G06F12/0875

摘要： An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be sequentially retrieved beginning with a selected instruction. The selected instruction is offset from the first instruction of the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A selected instruction of the first plurality of instructions is identified within the first trace segment. The selected instruction is offset from the first instruction of the first trace segment. The offset information related to the position of the selected instruction within the first trace segment is stored. A method for retrieving cached instructions, wherein the cached instructions are stored in a trace segment and the trace segment has a head instruction, includes determining a linear address related to a selected instruction to be retrieved. An entry point into the trace segment corresponding to the linear address is identified. The entry point is offset from the head instruction. The selected instruction is retrieved from the entry point within the identified trace segment.

摘要翻译： 一种装置包括数据阵列和控制逻辑。 控制逻辑耦合到数据阵列并且适于将指令的至少一个跟踪段存储到数据阵列中。 控制逻辑允许从所选择的指令开始顺序检索跟踪段的指令。 所选择的指令偏离跟踪段的第一条指令。 用于缓存指令的方法包括将第一多个指令存储在第一跟踪段中。 所述第一多个指令的选择指令在所述第一跟踪段内被识别。 所选择的指令偏离第一个跟踪段的第一个指令。 存储与第一跟踪段内的所选指令的位置相关的偏移信息。 一种用于检索高速缓存指令的方法，其中所述高速缓存指令被存储在跟踪段中，并且所述跟踪段具有头指令，包括确定与所选择的要被检索的指令相关的线性地址。 识别与线性地址对应的跟踪段的入口点。 入口点与头指令偏移。 从所识别的跟踪段中的入口点检索所选择的指令。

公开(公告)号：US4858464A

公开(公告)日：1989-08-22

申请号：US238570

申请日：1988-08-30

申请人： James J. Miller ,  Robert C. Valentine

发明人： James J. Miller ,  Robert C. Valentine

IPC分类号： G01M3/02 ,  G01M3/28

CPC分类号： G01M3/2846 ,  G01M3/022

摘要： The present disclosure is directed to a portable elongate frame made of multiple lengthwise stringers which support the pipe testing apparatus. The frame has upper and lower stringers which are laced together by cross connected braces, and said stringers assemble into an elongate structure having first and second carriages at opposite ends thereof. The two carriages support first and second test heads for the pin and box of the joint. They are equipped with resilient members which squeeze against the pipe, contact the joint on the interior on the pin end, and on the exterior at the coupling at the box end. The structure is formed of multiple lengthwise stringers, the stringers at one side being hinged, and the stringers at the opposite side being released by a latch means to enable the structure to be folded into two equal portions for easy mounting behind a tow vehicle connected therewith by a V-shaped trailer hitch.

摘要翻译： 本公开涉及一种由支撑管道测试装置的多个纵向纵梁制成的便携式细长框架。 框架具有通过交叉连接的支架嵌合在一起的上下桁条，并且所述桁条组装成具有在其相对端处的第一和第二托架的细长结构。 两个支架支撑用于接头销和箱的第一和第二测试头。 它们配备有弹性构件，该弹性构件挤压在管子上，与销端部内部的接头接触，并在箱体端部的联接器的外部接触。 该结构由多个纵向桁条形成，一侧的桁条被铰接，并且相对侧的桁条被一个锁紧装置释放，以使该结构能够被折叠成两个相等的部分，以便容易地安装在与之相连的牵引车辆后面 通过V型拖车搭便车。

公开(公告)号：US20150277532A1

公开(公告)日：2015-10-01

申请号：US14225612

申请日：2014-03-26

申请人： MICHAEL MISHAELI ,  RON GABOR ,  ROBERT C. VALENTINE ,  ALEX GERBER ,  ZEEV SPERBER

发明人： MICHAEL MISHAELI ,  RON GABOR ,  ROBERT C. VALENTINE ,  ALEX GERBER ,  ZEEV SPERBER

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

摘要： Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

摘要翻译： 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。 主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。 主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地 并且继续执行第一功率感知操作，而不等待本地门控电路被加电。

公开(公告)号：US20120254593A1

公开(公告)日：2012-10-04

申请号：US13078901

申请日：2011-04-01

申请人： Jesus Corbal San Adrian ,  Bret Toll ,  Robert C. Valentine ,  Milind Baburao Girkar ,  Andrew Thomas Foryth ,  George Z. Chrysos ,  Edward Thomas Grochowski ,  Dennis R. Bradford

发明人： Jesus Corbal San Adrian ,  Bret Toll ,  Robert C. Valentine ,  Milind Baburao Girkar ,  Andrew Thomas Foryth ,  George Z. Chrysos ,  Edward Thomas Grochowski ,  Dennis R. Bradford

IPC分类号： G06F9/38 ,  G06F9/312

CPC分类号： G06F9/324 ,  G06F9/30018 ,  G06F9/30058 ,  G06F9/30094

摘要： Embodiments of systems, apparatuses, and methods for performing a jump instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a conditional jump to an address of a target instruction when all of bits of a writemask are zero, wherein the address of the target instruction is calculated using an instruction pointer of the instruction and the relative offset.

摘要翻译： 描述了用于在计算机处理器中执行跳转指令的系统，装置和方法的实施例。 在一些实施例中，当写入掩码的所有位都为零时，混合指令的执行导致到目标指令的地址的条件跳转，其中使用指令的指令指针和相关的指令来计算目标指令的地址 抵消。

公开(公告)号：US20120254591A1

公开(公告)日：2012-10-04

申请号：US13078891

申请日：2011-04-01

申请人： Christopher J. Hughes ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Bret Toll ,  Robert C. Valentine ,  Milind Baburao Girkar ,  Andrew Thomas Foryth ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall

发明人： Christopher J. Hughes ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Bret Toll ,  Robert C. Valentine ,  Milind Baburao Girkar ,  Andrew Thomas Foryth ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall

IPC分类号： G06F9/312

摘要： Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask.

摘要翻译： 描述了用于在计算机处理器中执行收集和散播步幅指令的系统，装置和方法的实施例。 在一些实施例中，根据写入掩码的位值的至少一些，执行收集步幅指令导致从存储器进入到目的地寄存器的条带数据元素的有条件存储。

公开(公告)号：US06725362B2

公开(公告)日：2004-04-20

申请号：US09776849

申请日：2001-02-06

申请人： Opher D. Kahn ,  Robert C. Valentine

发明人： Opher D. Kahn ,  Robert C. Valentine

IPC分类号： G06F9312

CPC分类号： G06F9/3861 ,  G06F9/30043 ,  G06F9/30072

摘要： The present invention relates to a method and system for providing a load with conditional fault instruction that includes an associated conditional operator, which enables load operations to be advanced above program branches by the compiler without causing unwarranted fault conditions. Specifically, the load instruction can be executed out of normal program order to enable information to be retrieved from memory before the information is needed, to permit the retrieved information to begin to be used before the conditional operator can be evaluated. Likewise, a dynamically scheduled processor can advance components of the instruction and further improve performance without having faults effect the normal program flow. The load instruction can stop the use of the information and replace the information with a predetermined, generally deterministic, value if the conditional operator indicates a faulty load operation.

摘要翻译： 本发明涉及一种用于向负载提供条件故障指令的方法和系统，所述条件故障指令包括相关联的条件运算符，其使加载操作能够在编译器之上超过程序分支，而不引起无理的故障状况。 具体地说，可以按正常的程序顺序执行加载指令，以使得能够在需要信息之前从存储器检索信息，以便在可以评估条件运算符之前开始使用所检索的信息。 类似地，动态调度的处理器可以推进指令的组件，并进一步提高性能，而不会使故障影响正常的程序流程。 如果条件操作员指示故障加载操作，则加载指令可以停止使用信息并以预定的，通常确定的值替换信息。

公开(公告)号：US5987595A

公开(公告)日：1999-11-16

申请号：US977546

申请日：1997-11-25

申请人： Adi Yoaz ,  Ronny Ronen ,  Robert C. Valentine

发明人： Adi Yoaz ,  Ronny Ronen ,  Robert C. Valentine

IPC分类号： G06F9/38 ,  G06F9/312

CPC分类号： G06F9/3834 ,  G06F9/383 ,  G06F9/3838

摘要： The invention in several embodiments includes an apparatus and a method for predicting whether store instructions can be safely executed out-of-order. The apparatus, includes at least one execution unit, a reorder buffer adapted to holding a plurality of instructions from an instruction sequence for execution by the execution units, and a memory storage device adapted to holding a collision history table. The collision history table has entries for load instructions of the instruction sequence Each of the entries is adapted to predicting when the associated load instruction is colliding.

摘要翻译： 在几个实施例中的本发明包括一种用于预测存储指令是否可以无序安全执行的装置和方法。 该装置包括至少一个执行单元，适于从执行单元执行的指令序列保持多个指令的重排序缓冲器，以及适于保持冲突历史表的存储器存储装置。 冲突历史表具有用于指令序列的加载指令的条目每个条目适于预测何时相关联的加载指令相冲突。

公开(公告)号：US20140149724A1

公开(公告)日：2014-05-29

申请号：US14170397

申请日：2014-01-31

申请人： Robert C. Valentine ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert D. Cavin ,  Bret L. Toll ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall ,  Dennis R. Bradford ,  Elmoustapha Ould-Ahmed-Vall ,  James C. Abel ,  Mark Charney ,  Seth Abraham ,  Suleyman Sair ,  Andrew Thomas Forsyth ,  Lisa Wu ,  Charles Yount

发明人： Robert C. Valentine ,  Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert D. Cavin ,  Bret L. Toll ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Edward Thomas Grochowski ,  Jonathan Cannon Hall ,  Dennis R. Bradford ,  Elmoustapha Ould-Ahmed-Vall ,  James C. Abel ,  Mark Charney ,  Seth Abraham ,  Suleyman Sair ,  Andrew Thomas Forsyth ,  Lisa Wu ,  Charles Yount

IPC分类号： G06F9/30

CPC分类号： G06F9/30181 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34

摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

摘要翻译： 一种向量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 指令集包括向量友好指令格式。 向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作， 基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

公开(公告)号：US20120254592A1

公开(公告)日：2012-10-04

申请号：US13078896

申请日：2011-04-01

申请人： Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert C. Valentine ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Andrew Thomas Forsyth ,  Victor W. Lee

发明人： Jesus Corbal San Adrian ,  Roger Espasa Sans ,  Robert C. Valentine ,  Santiago Galan Duran ,  Jeffrey G. Wiedemeier ,  Sridhar Samudrala ,  Milind Baburao Girkar ,  Andrew Thomas Forsyth ,  Victor W. Lee

IPC分类号： G06F9/30

CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

摘要： Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.

摘要翻译： 描述了用于在计算机处理器中执行展开和/或压缩指令的系统，装置和方法的实施例。 在一些实施例中，扩展指令的执行导致根据写入掩码的值来稀疏地存储在目的地的源的元素的选择，并将源的每个选择的数据元素作为稀疏数据元素存储到目的地 位置，其中目的地位置对应于指示要存储源的相应数据元素的每个写入位位置。