公开(公告)号：US20060076613A1

公开(公告)日：2006-04-13

申请号：US11206212

申请日：2005-08-18

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Malhan

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Malhan

IPC: H01L29/94

CPC classification number: H01L29/1066 ,  H01L29/7722 ,  H01L29/8083

Abstract: A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.

Abstract translation: 半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽， 沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极 控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管， 在第二沟槽之间的第二表面上形成的结。

公开(公告)号：US20050233539A1

公开(公告)日：2005-10-20

申请号：US11105587

申请日：2005-04-14

Applicant: Yuuichi Takeuchi ,  Rajesh Malhan ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

Inventor： Yuuichi Takeuchi ,  Rajesh Malhan ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC: C30B23/02 ,  H01L21/04 ,  H01L21/306 ,  H01L21/337 ,  H01L21/76 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78 ,  H01L29/808

CPC classification number: H01L29/045 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/8083

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.

Abstract translation: 一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除 比1600℃

公开(公告)号：US20060205195A1

公开(公告)日：2006-09-14

申请号：US11159264

申请日：2005-06-23

Applicant: Rajesh Malhan ,  Yuichi Takeuchi ,  Irina Nikitina ,  Konstantin Vassilevski ,  Nicholas Wright ,  Alton Horsfall

Inventor： Rajesh Malhan ,  Yuichi Takeuchi ,  Irina Nikitina ,  Konstantin Vassilevski ,  Nicholas Wright ,  Alton Horsfall

IPC: H01L21/28

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395

Abstract: A method of forming an ohmic contact on a substrate composed of a wide-band gap semiconductor material includes: depositing a transition metal group metal on the substrate; annealing the substrate at a high temperature to cause a solid state chemical reaction between the substrate and the deposited metal that forms a modified layer in the substrate having modified properties different than the substrate, and by-products composed of a silicide and a nanocrystalline graphite layer; selectively etching the substrate to remove one or more of the by-products of the solid state chemical reaction from a surface of the substrate; and depositing a metal film composed of a transition group metal over the modified layer on the substrate to form the ohmic contact. The modified layer permits formation of the ohmic contact without high temperature annealing after depositing the metal film.

Abstract translation: 在由宽带隙半导体材料构成的衬底上形成欧姆接触的方法包括：在衬底上沉积过渡金属组金属; 在高温下使基板退火，从而在基板和沉积金属之间产生固态化学反应，所述金属在衬底中形成改性的特性，其具有不同于衬底的改性，以及由硅化物和纳米晶体石墨层组成的副产物 ; 选择性地蚀刻所述基板以从所述基板的表面去除所述固态化学反应的一种或多种副产物; 以及在所述基板上在所述改性层上沉积由过渡金属组成的金属膜以形成欧姆接触。 在沉积金属膜之后，改性层允许形成欧姆接触而不进行高温退火。

公开(公告)号：US20070221924A1

公开(公告)日：2007-09-27

申请号：US11802810

申请日：2007-05-25

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

IPC: H01L29/772

CPC classification number: H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

Abstract translation: 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。

公开(公告)号：US20060060884A1

公开(公告)日：2006-03-23

申请号：US11138298

申请日：2005-05-27

Applicant: Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

Inventor： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Rajesh Malhan ,  Tsuyoshi Yamamoto ,  Toshiyuki Morishita

IPC: H01L29/74

CPC classification number: H01L29/66416 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/8083

Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

Abstract translation: 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。