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1.发明授权Interface for controlling information transfers between main data processing systems units and a central subsystem 失效用于控制主数据处理系统单元和中央子系统之间的信息传输的接口
公开(公告)号：US4371928A
公开(公告)日：1983-02-01
申请号：US140623
申请日：1980-04-15
CPC分类号： G06F12/04 , G06F13/1678
摘要： In a data processing system, a system memory includes first memory modules having a data path of a first bit width and second memory modules having a data path of a second bit width with the first bit width being less than the second bit width. A central subsystem includes a cache memory unit and processing units for initiating requests for data transfers of the second bit width between the system memory and the subsystem processing units. An interface coupling the system memory and the central subsystem for bidirectional data transfers generates, in response to a memory request of a second bit width wherein the requested data is stored in a first memory module, additional memory requests until sufficient data has been retrieved from the system memory to satisfy the central subsystem request. The interface also monitors data transfers between the system processing units and the system memory and transfers the data transfers to the central subsystem in order to update and to retain the integrity of the cache memory in the central subsystem.
摘要翻译： 在数据处理系统中，系统存储器包括具有第一位宽度的数据路径的第一存储器模块和具有第二位宽度的数据路径的第二存储器模块，第一位宽小于第二位宽度。 中央子系统包括高速缓冲存储器单元和处理单元，用于启动系统存储器和子系统处理单元之间的第二位宽的数据传输请求。 耦合系统存储器和用于双向数据传输的中央子系统的接口响应于第二位宽度的存储器请求而产生其中所请求的数据存储在第一存储器模块中的附加存储器请求，直到从 系统内存以满足中央子系统的要求。 该接口还监视系统处理单元和系统存储器之间的数据传输，并将数据传输传送到中央子系统，以便更新并保持高速缓冲存储器在中央子系统中的完整性。
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公开(公告)号：US4424561A
公开(公告)日：1984-01-03
申请号：US221854
申请日：1980-12-31
CPC分类号： G06F12/0851
摘要： A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.
摘要翻译： 一种在数据处理系统中使用的高速缓存存储器，其中由偶数地址号码识别的数据字与与奇数地址号码相关联的数据字分开存储，以使得能够通过传送 与奇数地址号码相关联的数据字和与偶数地址号码相关联的数据字。
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公开(公告)号：US4451883A
公开(公告)日：1984-05-29
申请号：US326260
申请日：1981-12-01
CPC分类号： G06F9/30032 , G06F9/30167
摘要： A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.
摘要翻译： 数据处理系统包括用于存储操作数和指令的存储器子系统和用于通过执行指令来操纵操作数的中央处理单元（CPU）。 CPU包括用于产生用于控制CPU操作的信号的控制存储器。 由复用器组成的移位器响应于控制存储信号在外部总线和写入总线之间移动操作数。 多路复用器将操作数向左或向右移位1,2或4位位置，包括开位移和循环移位，并且还执行字节位移和孪生。
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公开(公告)号：US4438493A
公开(公告)日：1984-03-20
申请号：US280720
申请日：1981-07-06
摘要： A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by providing the address of the first of N consecutive words to be retrieved in parallel. The data is stored in memory in physical data words which contain N logical data words such that the addressing of one physical data word will result in N logical data words being read in parallel from the memory. Each physical data word contains the contents of the logical data word having the same address as that of the physical data word in its leftmost position followed in the next right position by the contents of the logical data word having the next higher address, and so on until the rightmost position of the physical data word contains the contents of the logical data word with an address equal to the physical data word address plus N-1. This results in the contents of each logical data word being stored N times in the memory, but eliminates the need for data alignment as the N logical data words are read in parallel from the memory.
摘要翻译： 公开了一种用于存储数据并将存储的数据寻址到并行地检索多个数据字的存储器中的技术和装置。 通过提供并行检索的N个连续字中的第一个字的地址来寻址存储器。 将数据存储在存储有包含N个逻辑数据字的物理数据字中，使得一个物理数据字的寻址将导致从存储器并行读取的N个逻辑数据字。 每个物理数据字包含具有与其最左侧位置的物理数据字的地址相同的地址的逻辑数据字的内容，紧接在下一个右侧位置，具有具有下一个较高地址的逻辑数据字的内容，等等 直到物理数据字的最右边位置包含地址等于物理数据字地址加N-1的逻辑数据字的内容。 这导致每个逻辑数据字的内容在存储器中被存储N次，但是当N个逻辑数据字从存储器并行读取时，不需要数据对准。
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公开(公告)号：US4079451A
公开(公告)日：1978-03-14
申请号：US674698
申请日：1976-04-07
CPC分类号： G06F9/30018 , G06F12/04
摘要： A data processing system for providing word, byte or bit addressing. A word location in a memory device may be addressed based upon the contents of a base address register. Indirect addressing may be provided to another word location based upon a word index value in an index register. Effective byte or bit addressing of the addressed word is provided in response to byte and bit index values which are produced by means of the index register. An instruction word indicates the type of addressing and directs the use of different control words included in a control storage device in order to implement the desired operation.
摘要翻译： 一种用于提供字，字节或位寻址的数据处理系统。 可以基于基地址寄存器的内容来寻址存储器设备中的字位置。 可以基于索引寄存器中的单词索引值将间接寻址提供给另一单词位置。 响应于通过索引寄存器产生的字节和位索引值，提供寻址字的有效字节或位寻址。 指令字指示寻址的类型并指示使用包括在控制存储设备中的不同控制字，以便实现期望的操作。
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公开(公告)号：US4467417A
公开(公告)日：1984-08-21
申请号：US302903
申请日：1981-09-16
CPC分类号： G06F9/30181 , G06F9/3016 , G06F9/325
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
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7.发明授权
公开(公告)号：US4349874A
公开(公告)日：1982-09-14
申请号：US140630
申请日：1980-04-15
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit. The requested procedural data words and non-procedural data words are transferred to the central processing unit by an interfacing device including a data bus latch for receiving the procedural data words and non-procedural data words transferred from the memory, a prefetch buffer for storing up to four words, a first set of OR gate circuits for selectively transferring the procedural data words stored in the prefetch buffer to a procedural data multiplexer for assembling either a procedural data word or a procedure address, and a second set of OR gate circuits for selectively transferring either a procedural data word or non-procedural data word to the source bus or a procedural data address or non-procedural data address to the source bus for transfer to the central processor unit.
摘要翻译： 在数据处理系统中，中央处理器单元请求存储在系统存储器中的过程数据字或非程序数据字。 控制存储设备执行固件指令，其包括本地总线字段，用于控制所请求的过程数据字和非程序数据字向中央处理器单元的传送。 所请求的程序数据字和非程序数据字通过包括用于接收程序数据字的数据总线锁存器和从存储器传送的非程序数据字的接口装置传送到中央处理器，用于存储的预取缓冲器 四个字，第一组OR门电路，用于选择性地将存储在预取缓冲器中的程序数据字传送到程序数据多路复用器，用于组装程序数据字或程序地址，以及第二组OR门电路，用于选择性地 将程序数据字或非程序数据字传送到源总线或程序数据地址或非程序数据地址到源总线以传送到中央处理器单元。
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公开(公告)号：US4241418A
公开(公告)日：1980-12-23
申请号：US854301
申请日：1977-11-23
申请人： Philip E. Stanley
发明人： Philip E. Stanley
摘要： A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.
摘要翻译： 一种用于提供矩形波形或波列的时钟系统，每个波段具有可选择的预定时钟周期周期。 由发生器产生矩形波列，该发生器包括耦合到逆变器的延迟线。 通过使用第二延迟线将矩形波延迟可选择的预定延迟周期，形成控制信号，当控制信号被馈送到发生器中时，产生具有等于矩形波时钟周期周期的时钟周期周期的第二矩形波列 加上第二预定延迟的周期。 添加同步电路允许在时钟周期期间动态地选择时钟周期周期。 这提供了一个矩形列，其中每个时钟周期的周期是与前一个或后续时钟周期的时钟周期周期无关的任何预定时钟周期。
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公开(公告)号：US4047247A
公开(公告)日：1977-09-06
申请号：US674517
申请日：1976-04-07
CPC分类号： G06F9/355
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址在微程序数据处理系统中通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 寻址的控制存储字提供用于控制系统操作的信号，包括在诸如指令获取，寻址，读取，写入和执行之类的主要操作之间的分支以及在主要操作中包括的次要操作之间的分支。
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10.发明授权Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit 失效通过使用中央处理器单元中的数据类型字段对扩展整数和商业指令处理器指令进行微编程控制
公开(公告)号：US4491908A
公开(公告)日：1985-01-01
申请号：US326442
申请日：1981-12-01
CPC分类号： G06F9/30192 , G06F9/26 , G06F9/268
摘要： A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.
摘要翻译： 数据处理系统包括执行指令的微程序控制的中央处理单元。 指令字包括用于识别在执行指令期间处理的操作数的类型的数据类型字段。 数据类型场信号和多个控制信号被施加到只读存储器的地址端子。 只读存储器输出信号由微程序的微字测试以分支到固件例程以处理操作数类型。
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