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公开(公告)号：US08917083B2
公开(公告)日：2014-12-23
申请号：US12953810
申请日：2010-11-24
CPC分类号： G01R27/28 , G01R23/20 , G01R35/00 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.
摘要翻译： 提供射频（RF）去嵌入的电气结构，方法和计算机程序产品。 一种结构包括第一测试装置，对应于第一测试装置的第一穿透结构以及对应于第一测试装置的第一开放结构。 该结构还包括具有与第一测试装置至少一个不同的物理尺寸但与第一测试装置相同的第二测试装置，对应于第二测试装置的第二穿透结构以及对应于第二测试的第二开放结构 设备。 一种方法包括：基于第一和第二DUT结构的测量电参数，通过结构，确定第二DUT结构中的第一测试设备的第一测试设备的第一电参数和第二DUT结构中的第二电参数， 和开放结构。
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2.发明授权公开(公告)号：US08754736B2
公开(公告)日：2014-06-17
申请号：US13012027
申请日：2011-01-24
CPC分类号： H01F17/0013 , H01F2017/0073 , H01F2017/0086
摘要： Disclosed is an inductor structure. The inductor structure includes a base material, at least one bottom spiral conductor disposed on the base material, a middle spiral conductor disposed on the bottom spiral conductor, a top spiral conductor disposed on the middle spiral conductor, and dielectric material separating the bottom, middle and top spiral conductors. The at least one bottom spiral conductor is connected electrically in parallel to the middle spiral conductor and the middle spiral conductor is connected electrically in series to the top spiral conductor. The top spiral conductor is thicker, narrower and less tightly wound than the middle spiral conductor and the bottom spiral conductor.
摘要翻译： 公开了电感器结构。 电感器结构包括基材，至少一个设置在基材上的底部螺旋导体，设置在底部螺旋导体上的中间螺旋导体，设置在中间螺旋导体上的顶部螺旋导体，以及将底部，中间 和顶部螺旋导体。 所述至少一个底部螺旋导体与所述中间螺旋导体并联地电连接，并且所述中间螺旋导体与所述顶部螺旋导体串联连接。 顶部螺旋导体比中间螺旋导体和底部螺旋导体更厚，更窄，更紧密地缠绕。
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公开(公告)号：US20120126792A1
公开(公告)日：2012-05-24
申请号：US12953810
申请日：2010-11-24
IPC分类号： G01R19/00
CPC分类号： G01R27/28 , G01R23/20 , G01R35/00 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.
摘要翻译： 提供射频（RF）去嵌入的电气结构，方法和计算机程序产品。 一种结构包括第一测试装置，对应于第一测试装置的第一穿透结构以及对应于第一测试装置的第一开放结构。 该结构还包括具有与第一测试装置至少一个不同的物理尺寸但与第一测试装置相同的第二测试装置，对应于第二测试装置的第二穿透结构以及对应于第二测试的第二开放结构 设备。 一种方法包括：基于第一和第二DUT结构的测量电参数，通过结构，确定第二DUT结构中的第一测试设备的第一测试设备的第一电参数和第二DUT结构中的第二电参数， 和开放结构。
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4.发明授权公开(公告)号：US07602265B2
公开(公告)日：2009-10-13
申请号：US11163485
申请日：2005-10-20
申请人： Hariklia Deligianni , Robert D. Edwards , Thomas J. Fleischman , Robert A. Groves , Charles J. Montrose , Richard P. Volant , Ping-Chuan Wang
发明人： Hariklia Deligianni , Robert D. Edwards , Thomas J. Fleischman , Robert A. Groves , Charles J. Montrose , Richard P. Volant , Ping-Chuan Wang
IPC分类号： H01H51/22
CPC分类号： H01H59/0009
摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.
摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。
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公开(公告)号：US06720230B2
公开(公告)日：2004-04-13
申请号：US10238746
申请日：2002-09-10
申请人： Raul E. Acosta , Melanie L. Carasso , Steven A. Cordes , Robert A. Groves , Jennifer L. Lund , Joanna Rosner
发明人： Raul E. Acosta , Melanie L. Carasso , Steven A. Cordes , Robert A. Groves , Jennifer L. Lund , Joanna Rosner
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01F17/0006 , H01F17/0033 , H01F41/041 , H01L27/08
摘要： A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.
摘要翻译： 提供一种用于制造集成在半导体芯片中的螺线管电感器的装置。 螺线管线圈部分地嵌入到蚀刻到芯片衬底中的深阱中。 线圈的非嵌入部分被制造为BEOL金属化层的一部分。 这允许螺线管的大的横截面积的匝数，从而减少匝间电容耦合。 由于本发明的螺线管线圈具有大直径的横截面，所以线圈可以制造成具有大的电感值，并且占据芯片的小面积。 所述制造工艺包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质衬里所述空腔，然后制造将通过掩模沉积导电材料金属而嵌入的线圈部分; 通过CMP沉积其相同的电介质和平面化。 在平坦化之后，螺线管线圈的剩余部分的制造被制造为BEOL中的金属化的一部分（即，作为BEOL的线/通路）。 为了进一步增加螺线管线圈的横截面，可以通过电沉积通过BEOL层顶部的掩模来构建。
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公开(公告)号：US06714113B1
公开(公告)日：2004-03-30
申请号：US09712369
申请日：2000-11-14
申请人： Wagdi Abadeer , Robert A. Groves , Patrick Hansen
发明人： Wagdi Abadeer , Robert A. Groves , Patrick Hansen
IPC分类号： H01F2728
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An inductor is integrated in VLSI and ULSI technology products for very high frequency applications. The inductor is in a microstrip transmission line configuration which can be designed in a form of straight line, spiral line or Meander line. The inductor is formed by shorting the microstrip center conductor to the lower level ground plane at one end of the transmission line. This results in an inductance which, for a given design of transmission line, and in a specified frequency range, is independent of frequency, within the operating design range. The microstrip transmission line provides an inductance which could be used on any type of substrate, with either low or high resistivity. The microstrip transmission line could utilize two or all of the metal wiring levels of the technology, allowing a wide range of inductance and quality factor design tradeoffs. An important feature in this trade-off is the ability to utilize lower (below the inductor) metal wiring levels, as well as lower silicon and polysilicon areas for other than inductor design purposes, without affecting the operation of the inductor. This is because of the isolation properties of this inductor system. By utilizing isolation layers with low relative dielectric constant, Further enhancements of the system are achieved. The inductance of this system is constant within 10% over a frequency range extending from about 8 GHz to about 35 GHz This inductor system allows the design to be optimized, through several parameters, to achieve the desired performance.
摘要翻译： 电感器集成在VLSI和ULSI技术产品中，适用于非常高频率的应用。 电感器处于微带传输线配置中，可以以直线，螺旋线或曲折线的形式设计。 电感器通过在传输线的一端将微带中心导体短路到下层接地平面而形成。 这导致对于给定的传输线设计并且在指定的频率范围内，在操作设计范围内的电感是独立于频率的。 微带传输线提供可用于任何类型的基板的电感，具有低或高电阻率。 微带传输线可以利用该技术的两个或所有金属布线级别，允许广泛的电感和品质因数设计权衡。 这种折衷的一个重要特征是能够利用低于（电感）以下的金属布线水平，以及除了电感器设计目的之外的较低的硅和多晶硅区域，而不会影响电感器的工作。 这是因为这个电感系统的隔离性能。 通过利用具有低相对介电常数的隔离层，实现了系统的进一步增强。 该系统的电感在从大约8 GHz到大约35 GHz的频率范围内恒定在10％以内。该电感系统允许通过几个参数优化设计以实现所需的性能。
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公开(公告)号：US06489857B2
公开(公告)日：2002-12-03
申请号：US09727165
申请日：2000-11-30
IPC分类号： H01P110
CPC分类号： H01H59/0009 , H01H2001/0084
摘要： A micro electromechanical switch has a guidepost formed upon a substrate. A signal transmission line is formed on the substrate, with the signal transmission line having a gap and forming an open circuit. The switch further includes a switch body having a via opening formed therein, with the switch body being movably disposed along an length defined by the guide post. The guidepost is partially surrounded by the via opening.
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公开(公告)号：US06414371B1
公开(公告)日：2002-07-02
申请号：US09580130
申请日：2000-05-30
申请人： Gregory G. Freeman , Robert A. Groves , Jeffrey Johnson , Seshadri Subbanna , Richard P. Volant
发明人： Gregory G. Freeman , Robert A. Groves , Jeffrey Johnson , Seshadri Subbanna , Richard P. Volant
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L21/8222 , H01L27/0823
摘要： High frequency performance of transistor designs is enhanced and manufacturing yield improved by removing and reducing sources of parasitic capacitance through combinations of processes from different technologies. After formation of collector, base and emitter regions on a substrate and attachment of a second substrate, the original substrate is wholly or partially removed, the inactive collector area is removed or rendered semi-insulating and wiring and contacts are made from the original back side of the chip. Dielectric material used in the manufacturing process can be removed to further reduce capacitance. The high frequency transistors can be bonded to CMOS chips or wafers to form BICMOS chips.
摘要翻译： 提高了晶体管设计的高频性能，并通过不同技术的工艺组合来去除和减少寄生电容源，从而提高了制造成品率。 在衬底上形成集电极，基极和发射极区域并附接第二衬底后，原始衬底被全部或部分去除，非活性集电极区域被去除或呈半绝缘，并且布线和接触由原始背面制成 的芯片。 可以去除在制造过程中使用的介电材料，以进一步降低电容。 高频晶体管可以结合到CMOS芯片或晶圆上以形成BICMOS芯片。
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9.发明授权Capturing mutual coupling effects between an integrated circuit chip and chip package 有权捕获集成电路芯片和芯片封装之间的互耦效应公开(公告)号：US08640077B1
公开(公告)日：2014-01-28
申请号：US13561760
申请日：2012-07-30
申请人： Robert A. Groves , Wan Ni , Stephen A. St. Onge , Jiansheng Xu
发明人： Robert A. Groves , Wan Ni , Stephen A. St. Onge , Jiansheng Xu
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/82
摘要： Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters.
摘要翻译： 提供了使用电子设计自动化（EDA）工具捕获集成电路芯片和芯片封装之间的互耦效应的系统和方法。 具体地说，提供了一种在用于设计集成电路芯片的计算机基础设施中实现的方法。 该方法包括编译描述芯片封装耦合和集成电路芯片封装的电气行为的工艺技术参数。 该方法还包括生成寄生技术文件以包括编译过程技术参数。
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10.发明申请公开(公告)号：US20120188047A1
公开(公告)日：2012-07-26
申请号：US13012027
申请日：2011-01-24
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F2017/0073 , H01F2017/0086
摘要： Disclosed is an inductor structure. The inductor structure includes a base material, at least one bottom spiral conductor disposed on the base material, a middle spiral conductor disposed on the bottom spiral conductor, a top spiral conductor disposed on the middle spiral conductor, and dielectric material separating the bottom, middle and top spiral conductors. The at least one bottom spiral conductor is connected electrically in parallel to the middle spiral conductor and the middle spiral conductor is connected electrically in series to the top spiral conductor. The top spiral conductor is thicker, narrower and less tightly wound than the middle spiral conductor and the bottom spiral conductor.
摘要翻译： 公开了电感器结构。 电感器结构包括基材，至少一个设置在基材上的底部螺旋导体，设置在底部螺旋导体上的中间螺旋导体，设置在中间螺旋导体上的顶部螺旋导体，以及将底部，中间 和顶部螺旋导体。 所述至少一个底部螺旋导体与所述中间螺旋导体并联地电连接，并且所述中间螺旋导体与所述顶部螺旋导体串联连接。 顶部螺旋导体比中间螺旋导体和底部螺旋导体更厚，更窄，更紧密地缠绕。
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