公开(公告)号：US08671258B2

公开(公告)日：2014-03-11

申请号：US13260709

申请日：2010-03-27

申请人： Ross Stenfort

发明人： Ross Stenfort

IPC分类号： G06F12/00

CPC分类号： G06F1/3234 ,  G06F1/30 ,  G06F3/0605 ,  G06F3/0661 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/14 ,  G06F2212/7201 ,  G06F2213/0038 ,  G11C5/141 ,  G11C29/02

摘要： Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge.

摘要翻译： 存储系统逻辑块地址（LBA）解除分配管理和数据硬化提高了性能，效率和使用效用。 可选地，以第一格式（例如，与第一协议相关联）的LBA解分配信息被转换为第二格式（例如，与第二协议相关联）。 第一协议的示例是小型计算机系统接口（SCSI）协议，第二协议的示例是高级技术附件（ATA）协议。 可选地，LBA解除分配状态信息由诸如固态盘（SSD）的存储设备确定，并且被传送到诸如启动器，扩展器或桥接器的另一设备。

公开(公告)号：US07305603B1

公开(公告)日：2007-12-04

申请号：US10762799

申请日：2004-01-21

申请人： Ross Stenfort

发明人： Ross Stenfort

IPC分类号： G01R31/28 ,  G06K5/04

CPC分类号： G01R31/318541

摘要： An apparatus for performing a boundary scan test is provided, along with method for integrating and operating the same. The apparatus includes an asynchronous flip-flop that has a data input, a data output, a system clock input, a set input, and a reset input. The apparatus also includes a test controller that has a test clock input, a first test data output, and a second test data output. The first test data output of the test controller is connected to the set input of the asynchronous flip-flop. In addition, the second test data output of the test controller is connected to the reset input of the asynchronous flip-flop. The test controller is configured to control the asynchronous flip-flop through the set input and the reset input. The apparatus for performing the boundary scan test avoids introduction of adverse delay and skew effects caused by multiplexing circuitry.

摘要翻译： 提供了一种用于执行边界扫描测试的装置，以及用于集成和操作边界扫描测试的方法。 该装置包括具有数据输入，数据输出，系统时钟输入，设定输入和复位输入的异步触发器。 该装置还包括具有测试时钟输入，第一测试数据输出和第二测试数据输出的测试控制器。 测试控制器的第一个测试数据输出连接到异步触发器的设定输入。 此外，测试控制器的第二测试数据输出连接到异步触发器的复位输入。 测试控制器配置为通过设置输入和复位输入来控制异步触发器。 用于执行边界扫描测试的装置避免引入由复用电路引起的不利的延迟和偏斜效应。

公开(公告)号：US07373541B1

公开(公告)日：2008-05-13

申请号：US10800048

申请日：2004-03-11

申请人： Ross Stenfort ,  John Packer

发明人： Ross Stenfort ,  John Packer

IPC分类号： G06F1/14

CPC分类号： G06F13/423

摘要： Broadly speaking, an apparatus and associated method of operation is provided for controlling alignment signal transmission in an electronic communication process. More specifically, a programmable control is provided for controlling transmission of alignment signals in either a Serial Attached SCSI (SAS) or Serial ATA (SATA) communication process. The programmable control includes a counter operated to sequentially modify a count value. When the count value is equal to a programmed alignment trigger value, the programmable control is configured to generate and transmit an alignment signal through the initiator transceiver to the target transceiver. Thus, the apparatus and associated method of operation controls a rate at which alignment signals are transmitted in a SAS/SATA communication process.

摘要翻译： 广义地讲，提供了一种用于在电子通信过程中控制对准信号传输的装置和相关操作方法。 更具体地，提供可编程控制以控制串行连接SCSI（SAS）或串行ATA（SATA）通信过程中的对准信号的传输。 可编程控制器包括一个计数器，用于顺序修改计数值。 当计数值等于编程的对准触发值时，可编程控制器被配置为通过启动器收发器生成并发送对准信号到目标收发器。 因此，装置和相关联的操作方法控制在SAS / SATA通信过程中发送对准信号的速率。

公开(公告)号：US07210090B1

公开(公告)日：2007-04-24

申请号：US10733152

申请日：2003-12-10

申请人： Ross Stenfort

发明人： Ross Stenfort

IPC分类号： H03M13/00

CPC分类号： H04L67/00 ,  H04L1/0061 ,  H04L69/324

摘要： Broadly speaking a method and an apparatus is disclosed for enabling vendor-specific communication between devices of a common vendor. More specifically, the present invention provides a method and an apparatus for using vendor-specific cyclic redundancy check (CRC) data to identify a communication as containing vendor-specific data. The method and apparatus of the present invention does not inhibit compatibility between the vendor device and another device operating in accordance with a standard communication protocol. Additionally, the method and apparatus of the present invention allows the devices of the common vendor to implement features and functionality that rely on efficient and protected vendor-specific communication.

摘要翻译： 广义地说，公开了一种用于在公共供应商的设备之间进行供应商特定通信的方法和装置。 更具体地，本发明提供一种用于使用供应商特定的循环冗余校验（CRC）数据来识别包含供应商特定数据的通信的方法和装置。 本发明的方法和装置不会抑制供应商设备和根据标准通信协议操作的另一设备之间的兼容性。 此外，本发明的方法和装置允许公共供应商的设备实现依赖于有效和受保护的供应商特定通信的特征和功能。

公开(公告)号：US07181562B1

公开(公告)日：2007-02-20

申请号：US10816338

申请日：2004-03-31

申请人： Ross Stenfort ,  John Packer

发明人： Ross Stenfort ,  John Packer

IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F7/38 ,  G06F13/12

CPC分类号： G06F13/4013 ,  G06F3/0661 ,  G06F3/0674

摘要： A method and associated apparatus is provided for operating an electronic device in accordance with a wired endian format. More specifically, the wired endian format requires multi-byte values be maintained in transmit order. The wired endian format is defined to allow for interfacing with both a big endian format and a little endian format. Thus, a device operating in accordance with the wired endian format is able to interface with both a device operating in accordance with the big endian format (e.g., a Serial Attached SCSI (SAS) device) and a device operating in accordance with the little endian format (e.g., a Serial ATA (SATA) device). Furthermore, since the device operating in accordance with wired endian format implements circuitry compliant with the wired endian format, duplication of circuitry to define separate data paths for interfacing with the big endian and little endian formats, respectively, is avoided.

摘要翻译： 提供了一种根据有线端格式操作电子设备的方法和相关设备。 更具体地说，有线端格式要求以发送顺序维持多字节值。 有线端格式被定义为允许与大端格式和小端格式的接口。 因此，根据有线端格式操作的设备能够与根据大端格式操作的设备（例如，串行连接SCSI（SAS）设备）和根据小端序号操作的设备进行接口 格式（例如，串行ATA（SATA）设备）。 此外，由于根据有线端格式操作的设备实现符合有线端格式的电路，所以避免了分别用于界定用于与大端和小端格式进行接口的单独数据路径的电路复制。

公开(公告)号：US06966022B1

公开(公告)日：2005-11-15

申请号：US10116922

申请日：2002-04-04

申请人： Ross Stenfort ,  Tianshu Chi

发明人： Ross Stenfort ,  Tianshu Chi

IPC分类号： G01R31/00 ,  G01R31/3185 ,  G11C8/00 ,  G11C29/50 ,  H03L7/00

CPC分类号： G11C29/50 ,  G01R31/318541 ,  G01R31/318594 ,  G11C29/50012

摘要： An invention is disclosed for determining integrated circuit (IC) logic speed. A storage element is provided that includes a reset input in electrical communication with a reset pin. A reset signal is then asserted at the reset pin, and a reset time is measured. The reset time is defined as the time period beginning when the reset signal is asserted and ending when the storage element resets. In this manner, the reset time can be used to determine a speed of the IC logic relative to a process. In one aspect, delay logic is provided that is in electrical communication with the reset pin and in electrical communication with the storage element. In this aspect, the delay logic delays the reset signal for a predetermined time period. Optionally, the reset time can be compared to a predetermined fast corner reset time and a predetermined slow corner reset time. Further, the IC logic speed can be correlated to a simulation using the embodiments of the present invention.

摘要翻译： 公开了一种用于确定集成电路（IC）逻辑速度的发明。 提供一种存储元件，其包括与复位引脚电连通的复位输入。 然后，在复位引脚上确认复位信号，并测量复位时间。 复位时间被定义为当复位信号被断言并在存储元件复位时结束的时间段。 以这种方式，可以使用复位时间来确定IC逻辑相对于处理的速度。 在一个方面，提供延迟逻辑，其与复位引脚电连通并与存储元件电连通。 在这方面，延迟逻辑将复位信号延迟预定的时间段。 可选地，复位时间可以与预定的快速转角复位时间和预定的慢转角复位时间进行比较。 此外，IC逻辑速度可以与使用本发明的实施例的模拟相关。

公开(公告)号：US20180039411A1

公开(公告)日：2018-02-08

申请号：US15666094

申请日：2017-08-01

申请人： Ross Stenfort

发明人： Ross Stenfort

IPC分类号： G06F3/06 ,  G06F13/42 ,  G06F13/40

CPC分类号： G06F3/061 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0679 ,  G06F13/387 ,  G06F13/4027 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2213/3852

摘要： A non-volatile memory (“NVM”) solid state drive (“SSD”) auxiliary (“NSA”) plug, capable of providing bridge function and memory storage, is structured in a small form-factor pluggable (“SFP”) or quad small form-factor pluggable (“QSFP”) configuration. In one aspect, an SFP auxiliary plug (“SAP”) or NSA plug includes an Ethernet connector, NVM storage, bridge component, and memory controller. The Ethernet connector is pluggable to an Ethernet socket situated at a network system for data transmission. The NVM storage can store information persistently. The bridge component facilitates protocol conversion capable of converting data formatted between Ethernet protocol and a serial bus protocol for network communication. The memory controller is able to route data traffic between an output port of NSA plug and the NVM storage.

公开(公告)号：US07360119B1

公开(公告)日：2008-04-15

申请号：US10795183

申请日：2004-03-03

申请人： Ross Stenfort ,  Stillman Gates

发明人： Ross Stenfort ,  Stillman Gates

IPC分类号： G06F11/00

CPC分类号： G06F13/4291 ,  G06F11/0745 ,  G06F11/0757 ,  G06F11/0793

摘要： Broadly speaking, a method and apparatus is provided for identifying and responding to a deadlock condition in a SAS/SATA communication process. More specifically, an initiator device involved in the SAS/SATA communication process is defined to recognize a received error signal as an indication of a potential communication deadlock condition. The initiator device is further defined to promptly respond to the received error signal with a course of action for recovering from the communication deadlock condition.

摘要翻译： 概括而言，提供了一种用于识别和响应SAS / SATA通信过程中的死锁状态的方法和装置。 更具体地，涉及SAS / SATA通信处理的启动器设备被定义为将接收的错误信号识别为潜在的通信死锁状态的指示。 启动器设备被进一步定义为利用用于从通信死锁状态恢复的动作过程来迅速响应接收的错误信号。

公开(公告)号：US20120084492A1

公开(公告)日：2012-04-05

申请号：US13260709

申请日：2010-03-27

申请人： Ross Stenfort

发明人： Ross Stenfort

IPC分类号： G06F12/00

CPC分类号： G06F1/3234 ,  G06F1/30 ,  G06F3/0605 ,  G06F3/0661 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/14 ,  G06F2212/7201 ,  G06F2213/0038 ,  G11C5/141 ,  G11C29/02

摘要： Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge. Optionally, data stored on an SSD is hardened, such as in response to determining that the SSD is to be powered off. The hardening is via power supplied by an energy storage element, such as a super capacitor or a battery.

摘要翻译： 存储系统逻辑块地址（LBA）解除分配管理和数据硬化提高了性能，效率和使用效用。 可选地，以第一格式（例如，与第一协议相关联）的LBA解分配信息被转换为第二格式（例如，与第二协议相关联）。 第一协议的示例是小型计算机系统接口（SCSI）协议，第二协议的示例是高级技术附件（ATA）协议。 可选地，LBA解除分配状态信息由诸如固态盘（SSD）的存储设备确定，并且被传送到诸如启动器，扩展器或桥接器的另一设备。 可选地，存储在SSD上的数据被硬化，例如响应于确定SSD被断电。 硬化是通过诸如超级电容器或电池的能量存储元件提供的电力。

公开(公告)号：US07376759B1

公开(公告)日：2008-05-20

申请号：US10782249

申请日：2004-02-18

申请人： Ross Stenfort

发明人： Ross Stenfort

IPC分类号： G06F3/00 ,  G06F9/46 ,  G03F7/38

CPC分类号： G06F13/26

摘要： An apparatus and an associated method of operation is provided for performing device communication in accordance with a standard protocol, while enabling deviation from the device communication without termination or corruption of the device communication. The apparatus incorporates a pair of state machines configured to provide standard protocol communication with interrupt capability. A first state machine functions to perform the communication process in accordance with the standard protocol. The first state machine is also configured to deviate from the communication process in order to perform another requested task. A second state machine functions to monitor the communication process being performed by the first state machine. Upon completion of the other requested task by the first state machine, a state of the communication process is provided by the second state machine to enable the communication process to be continued by the first state machine.

摘要翻译： 提供了一种装置和相关联的操作方法，用于根据标准协议执行设备通信，同时能够在不终止或破坏设备通信的情况下实现与设备通信的偏差。 该装置包括配置成提供具有中断能力的标准协议通信的一对状态机。 第一状态机用于根据标准协议执行通信过程。 第一状态机还被配置为偏离通信进程以执行另一请求的任务。 第二状态机用于监视由第一状态机执行的通信过程。 在由第一状态机完成另一请求的任务时，由第二状态机提供通信处理的状态，以使第一状态机能够继续进行通信处理。