公开(公告)号：US08865835B2

公开(公告)日：2014-10-21

申请号：US13143803

申请日：2010-07-16

申请人： Kouichirou Taniguchi ,  Jun Nishioka ,  Ryota Yamamoto ,  Yo Miyashita

发明人： Kouichirou Taniguchi ,  Jun Nishioka ,  Ryota Yamamoto ,  Yo Miyashita

IPC分类号： H01L31/0203 ,  C09D153/00 ,  C08L53/00 ,  C08L23/04 ,  H01L31/048 ,  C08L23/08

CPC分类号： H01L31/048 ,  C08L23/0815 ,  C08L53/00 ,  C08L2203/204 ,  H01L31/0481 ,  Y02E10/50 ,  C08L2666/24

摘要： There is provided an encapsulant material for solar cells which facilitates production of a solar cell module and is excellent in flexibility, heat resistance, transparency, etc., and a solar cell module produced using the encapsulant material. The present invention relates to an encapsulant material for solar cells which includes a resin composition (C) containing an ethylene-α-olefin random copolymer (A) capable of satisfying the following condition (a) and an ethylene-α-olefin block copolymer (B) capable of satisfying the following condition (b): (a) a heat of crystal fusion is from 0 to 70 J/g as measured in differential scanning calorimetry at a heating rate of 10° C./min; and (b) a crystal fusion peak temperature is 100° C. or higher and a heat of crystal fusion is from 5 to 70 J/g as measured in differential scanning calorimetry at a heating rate of 10° C./min.

摘要翻译： 本发明提供一种太阳能电池用密封剂材料，该太阳能电池促进太阳能电池组件的制造，柔软性，耐热性，透明性等优异，以及使用该密封剂材料制造的太阳能电池组件。 本发明涉及一种太阳能电池用密封剂材料，其包含含有能够满足下述条件（a）的乙烯-α-烯烃无规共聚物（A）的树脂组合物（C）和乙烯-α-烯烃嵌段共聚物（ B）能够满足以下条件（b）：（a）在差示扫描量热法中以10℃/分钟的加热速率测量，结晶熔化热为0至70J / g; 和（b）以10℃/分钟的升温速度在差示扫描量热法中测定的结晶熔融峰温度为100℃以上，结晶熔融热为5〜70J / g。

公开(公告)号：US20130206214A1

公开(公告)日：2013-08-15

申请号：US13819163

申请日：2011-07-28

申请人： Osamu Akaike ,  Kouichirou Taniguchi ,  Michiko Otsuka ,  Jun Nishioka ,  Tetsuya Aya ,  Yo Miyashita ,  Ryota Yamamoto

发明人： Osamu Akaike ,  Kouichirou Taniguchi ,  Michiko Otsuka ,  Jun Nishioka ,  Tetsuya Aya ,  Yo Miyashita ,  Ryota Yamamoto

IPC分类号： H01L31/048

CPC分类号： H01L31/0481 ,  C08L23/0815 ,  C08L2203/204 ,  Y02E10/50 ,  C08L53/00

摘要： Provided is a cover film for solar cells, with which solar cell modules are easy to produce, which comprises an encapsulant resin layer excellent in softness, transparency and heat resistance, and a weather-resistant layer excellent in weather resistance, moisture proofness, transparency and heat resistance and having high adhesiveness to the encapsulant resin layer, and is therefore excellent in handleability, and which is effective for reducing the weight of solar cell modules and for enhancing the impact resistance and the durability thereof; and also provided is a solar cell module produced by the use of the cover film for solar cells. Disclosed is production of a cover film for solar cells by laminating weather-resistant layer or a surface protective layer, and an encapsulant resin layer comprising a resin composition that contains an ethylene-a-olefin random copolymer and an ethylene-α-olefin block copolymer both having specific thermal properties.

摘要翻译： 本发明提供一种太阳能电池用覆盖膜，太阳能电池模块易于制造，其包含柔软性，透明性和耐热性优异的密封树脂层，耐候性，耐湿性，透明性和耐候性优异的耐候层 耐热性高，与密封树脂层的粘合性高，因此处理性优异，对降低太阳能电池组件的重量和提高耐冲击性和耐久性是有效的。 并且还提供了通过使用太阳能电池用覆盖膜制造的太阳能电池模块。 公开了通过层叠耐候层或表面保护层的太阳能电池用覆盖膜的制造，以及包含含有乙烯-α-烯烃无规共聚物和乙烯-α-烯烃嵌段共聚物的树脂组合物的密封树脂层 两者都具有特定的热性能。

公开(公告)号：US20110254130A1

公开(公告)日：2011-10-20

申请号：US13173709

申请日：2011-06-30

申请人： Masayuki FURUMIYA ,  Kuniko KIKUTA ,  Ryota YAMAMOTO ,  Makoto NAKAYAMA

发明人： Masayuki FURUMIYA ,  Kuniko KIKUTA ,  Ryota YAMAMOTO ,  Makoto NAKAYAMA

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

摘要翻译： 半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。 第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

公开(公告)号：US20060231923A1

公开(公告)日：2006-10-19

申请号：US11455678

申请日：2006-06-20

申请人： Ryota Yamamoto ,  Masayuki Furumiya ,  Hiraoki Ohkubo ,  Yasutaka Nakashiba

发明人： Ryota Yamamoto ,  Masayuki Furumiya ,  Hiraoki Ohkubo ,  Yasutaka Nakashiba

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L28/10 ,  H01L21/76838 ,  H01L23/5227 ,  H01L23/53228 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.

公开(公告)号：US20050139956A1

公开(公告)日：2005-06-30

申请号：US11017695

申请日：2004-12-22

申请人： Hiroaki Ohkubo ,  Ryota Yamamoto ,  Masayuki Furumiya ,  Masaharu Sato ,  Kuniko Kikuta ,  Makoto Nakayama ,  Yasutaka Nakashiba

发明人： Hiroaki Ohkubo ,  Ryota Yamamoto ,  Masayuki Furumiya ,  Masaharu Sato ,  Kuniko Kikuta ,  Makoto Nakayama ,  Yasutaka Nakashiba

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/20 ,  H01L29/00

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

摘要翻译： 在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。 然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。 接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便 形成下电极和下布线。 以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

公开(公告)号：US06879234B2

公开(公告)日：2005-04-12

申请号：US10352048

申请日：2003-01-28

申请人： Masayuki Furumiya ,  Ryota Yamamoto ,  Jun Kishi ,  Hiroaki Ohkubo ,  Yasutaka Nakashiba

发明人： Masayuki Furumiya ,  Ryota Yamamoto ,  Jun Kishi ,  Hiroaki Ohkubo ,  Yasutaka Nakashiba

IPC分类号： H01F17/00 ,  H01F17/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H03B5/12 ,  H01F5/00 ,  H01F27/28

CPC分类号： H01L27/08 ,  H01F17/0006 ,  H01F2021/125 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124

摘要： Electrically conductive layers 1a and 2a connected to each other via a contact form one inductor, while electrically conductive layers 1b and 2b connected to each other via other contact form the other inductor. Since the areas defined by the loops forming these two inductors are equal to each other, the inductances of the inductors are also equal to each other. Between both the inductors, the lengths in the loop of the portions (the conductive layers 1a and 1b) formed on a lower interlayer insulating film are equal to each other, while the lengths in the loop of the portions (the conductive layers 2a and 2b) formed on an upper interlayer insulating film are also equal to each other. This allows external disturbances such as parasitic capacitance to affect both the inductors equally. Accordingly, a voltage controlled oscillator incorporating the invention can stably provide undistorted sinusoidal oscillation signals.

摘要翻译： 导电层1a和2a通过接触形成一个电感器，而导电层1b和2b通过其它触点相互连接形成另一个电感器。 由于由形成这两个电感器的环形成的区域彼此相等，所以电感器的电感也彼此相等。 在两个电感器之间，形成在下层间绝缘膜上的部分（导电层1a和1b）的环路中的长度彼此相等，而部分（导电层2a和2b）的环路中的长度 ）也相互相等。 这允许诸如寄生电容的外部干扰同样影响电感器。 因此，结合本发明的压控振荡器可以稳定地提供无失真的正弦振荡信号。

公开(公告)号：US20090189650A1

公开(公告)日：2009-07-30

申请号：US12320327

申请日：2009-01-23

申请人： Satoshi Fujino ,  Ryota Yamamoto

发明人： Satoshi Fujino ,  Ryota Yamamoto

IPC分类号： H02M11/00

CPC分类号： H03L7/0995 ,  H03L7/0891

摘要： A Phase-Locked Loop (PLL) circuit includes a voltage-controlled oscillator. The voltage-controlled oscillator includes a voltage-current conversion circuit and a current-controlled oscillation circuit. The voltage-current conversion circuit includes an input transistor having a gate terminal connecting a control voltage, a first transistor connected in series to the input transistor, a second transistor connected as a current-mirror to the first transistor, to generate a control current, and a current source connected in parallel to the first transistor. The current-controlled oscillation circuit oscillates at a frequency according to the control current.

摘要翻译： 锁相环（PLL）电路包括压控振荡器。 压控振荡器包括电压 - 电流转换电路和电流控制振荡电路。 电压 - 电流转换电路包括：输入晶体管，其具有连接控制电压的栅极端子，与输入晶体管串联连接的第一晶体管，连接到第一晶体管的电流镜的第二晶体管，以产生控制电流; 以及与第一晶体管并联连接的电流源。 电流控制振荡电路根据控制电流以频率振荡。

公开(公告)号：US20090051454A1

公开(公告)日：2009-02-26

申请号：US12222585

申请日：2008-08-12

申请人： Ryota Yamamoto

发明人： Ryota Yamamoto

IPC分类号： H03J7/04

CPC分类号： H01L21/823493 ,  H01L27/088 ,  H01L29/78

摘要： According to one aspect of the present invention, there is provided a voltage controlled oscillator controlling frequency of an output signal according to input voltage, the voltage controlled oscillator including a current controlled oscillator setting the frequency of the output signal based on control current, and a voltage-current converter including a transistor controlling a current amount of the control current according to the input voltage, in which the voltage-current converter is supplied with control voltage, and threshold value voltage of the transistor is controlled according to the control voltage.

摘要翻译： 根据本发明的一个方面，提供了一种根据输入电压控制输出信号频率的压控振荡器，所述压控振荡器包括基于控制电流设置输出信号频率的电流控制振荡器，以及 电压电流转换器包括根据输入电压控制控制电流的电流量的晶体管，其中电压电流转换器被提供控制电压，并且根据控制电压来控制晶体管的阈值电压。

公开(公告)号：US07432551B2

公开(公告)日：2008-10-07

申请号：US11362132

申请日：2006-02-27

申请人： Ryota Yamamoto ,  Yutaka Akiyama ,  Masayuki Furumiya

发明人： Ryota Yamamoto ,  Yutaka Akiyama ,  Masayuki Furumiya

IPC分类号： H01L27/01

CPC分类号： H01L21/84 ,  H01L21/761 ,  H01L21/76251 ,  H01L21/765 ,  H01L27/1203

摘要： An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor device, including: an SOI substrate in which a support substrate 10, an insulating layer 11, and an SOI layer 12 are stacked one by one; an element section 4 provided in one region of the SOI substrate; and a guard ring region 8 provided around the element section 4 of the SOI substrate, wherein a first diffusion layer 15 provided in the SOI layer 12 of the element section 4, and a second diffusion layer 26 provided in the SOI layer 12 of the guard ring region 8 are electrically connected to each other.

摘要翻译： 本发明的目的是增加保护环中吸收的衬底噪声的量，并且防止包括设置有保护环的SOI衬底的半导体器件中的衬底噪声引起的故障。 然后，提供一种半导体器件，包括：SOI衬底，其中支撑衬底10，绝缘层11和SOI层12一个一个地堆叠; 设置在SOI衬底的一个区域中的元件部分4; 以及设置在SOI衬底的元件部分4周围的保护环区域8，其中设置在元件部分4的SOI层12中的第一扩散层15和设置在护罩的SOI层12中的第二扩散层26 环形区域8彼此电连接。

公开(公告)号：US07339249B2

公开(公告)日：2008-03-04

申请号：US11066534

申请日：2005-02-28

申请人： Ryota Yamamoto ,  Yasutaka Nakashiba

发明人： Ryota Yamamoto ,  Yasutaka Nakashiba

IPC分类号： H01L29/00

CPC分类号： H01L21/765 ,  H01L21/761 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p type silicon substrate is formed as a non-doped region with no impurity implanted. Then, a positive power supply potential is applied to the electrode. In this way, a depletion layer is formed directly under the electrode at the surface of the p type silicon substrate. Consequently, the substrate noise is shielded.

摘要翻译： 在p型硅衬底上的电路区域周围的区域中设置绝缘膜，并且设置框状电极以围绕绝缘膜上的电路区域。 在p型硅衬底的表面的正下方的区域形成为没有杂质注入的非掺杂区域。 然后，向电极施加正电源电位。 以这种方式，在p型硅衬底的表面下方的电极正下方形成耗尽层。 因此，衬底噪声被屏蔽。