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8 条记录 (耗时 0.013 秒)

    Method of fabrication of on-chip heat pipes and ancillary heat transfer components
    1.
    发明授权
    Method of fabrication of on-chip heat pipes and ancillary heat transfer components 有权
    片上热管和辅助传热部件的制造方法

    公开(公告)号：US07781884B2

    公开(公告)日：2010-08-24

    申请号：US11863477

    申请日：2007-09-28

    申请人： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    发明人： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    IPC分类号： H01L23/34

    CPC分类号： H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

    摘要翻译： 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。

    Method of Fabrication of On-Chip Heat Pipes and Ancillary Heat Transfer Components
    3.
    发明申请
    Method of Fabrication of On-Chip Heat Pipes and Ancillary Heat Transfer Components 有权
    片上热管和辅助传热部件的制造方法

    公开(公告)号：US20090085197A1

    公开(公告)日：2009-04-02

    申请号：US11863477

    申请日：2007-09-28

    申请人： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    发明人： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

    IPC分类号： H01L23/34

    CPC分类号： H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

    摘要翻译： 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。

    Integration of pore sealing liner into dual-damascene methods and devices
    4.
    发明授权
    Integration of pore sealing liner into dual-damascene methods and devices 有权
    将密封衬垫整合到双镶嵌方法和装置中

    公开(公告)号：US07338893B2

    公开(公告)日：2008-03-04

    申请号：US11286877

    申请日：2005-11-23

    申请人： Edward Raymond Engbrecht ,  Satyavolu Srinivas Papa Rao ,  Sameer Kumar Ajmera ,  Stephan Grunow

    发明人： Edward Raymond Engbrecht ,  Satyavolu Srinivas Papa Rao ,  Sameer Kumar Ajmera ,  Stephan Grunow

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76844

    摘要： A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

    摘要翻译： 装置采用具有孔密封衬垫的镶嵌层，并且包括半导体本体。 包括金属互连的金属互连层形成在半导体本体上。 介电层形成在金属互连层上。 导电沟槽特征和导电通孔特征形成在电介质层中。 孔密封衬垫仅沿着导电通孔特征的侧壁并且沿着导电沟槽特征的侧壁和底表面形成。 孔密封衬垫基本上不存在于导电通孔特征的底表面上。

    Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect
    7.
    发明授权
    Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect 有权

    公开(公告)号：US07115467B2

    公开(公告)日：2006-10-03

    申请号：US10903712

    申请日：2004-07-30

    申请人： Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

    发明人： Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/75

    摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).