公开(公告)号：US07732324B2

公开(公告)日：2010-06-08

申请号：US11961464

申请日：2007-12-20

Applicant: Ju-Ai Ruan ,  Sameer K. Ajmera ,  Changming Jin ,  Anand J. Reddy ,  Tae S. Kim

Inventor： Ju-Ai Ruan ,  Sameer K. Ajmera ,  Changming Jin ,  Anand J. Reddy ,  Tae S. Kim

IPC: H01L21/469

CPC classification number: H01L23/53295 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).

Abstract translation: 本发明的一个方面提供了形成半导体器件（100）的方法。 一个方面包括在半导体衬底（105）上形成晶体管（120,125），在晶体管（120,125）之上形成第一层间电介质层（165），并在第一层间电介质内形成金属互连（170,175） 层（165）。 使用含碳气体在沉积工具内的金属互连（170,175）和第一层间介电层（165）上形成氮化硅（SiCN）层（180）。 通过中断沉积室内的含碳气体的流动，在沉积工具内在SiCN层（180）上形成粘附层（185）。 第二层间介质层（190）形成在粘合层（185）上方。

公开(公告)号：US20090115030A1

公开(公告)日：2009-05-07

申请号：US12330732

申请日：2008-12-09

Applicant: Sameer Kumar Ajmera ,  Patricia Beauregard Smith ,  Changming Jin

Inventor： Sameer Kumar Ajmera ,  Patricia Beauregard Smith ,  Changming Jin

IPC: H01L29/06

CPC classification number: H01L21/02126 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31058 ,  H01L21/31695 ,  H01L21/76801

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

Abstract translation: 一种形成半导体器件的方法，包括在衬底上形成低k电介质材料，在低k电介质材料的一部分上沉积衬垫，以及将衬套暴露于等离子体。 该方法还包括在衬垫上沉积层。

公开(公告)号：US20060172552A1

公开(公告)日：2006-08-03

申请号：US11046230

申请日：2005-01-31

Applicant: Sameer Ajmera ,  Patricia Smith ,  Changming Jin

Inventor： Sameer Ajmera ,  Patricia Smith ,  Changming Jin

IPC: H01L21/31

CPC classification number: H01L21/02126 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31058 ,  H01L21/31695 ,  H01L21/76801

Abstract: A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

公开(公告)号：US20050233586A1

公开(公告)日：2005-10-20

申请号：US10901708

申请日：2004-07-27

Applicant: Phillip Matz ,  Sameer Ajmera ,  Changming Jin ,  Trace Hurd

Inventor： Phillip Matz ,  Sameer Ajmera ,  Changming Jin ,  Trace Hurd

IPC: H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/02063 ,  H01L21/02052 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/7682

Abstract: A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.

Abstract translation: 在形成在硅衬底（10）上的低k电介质层（100）中形成沟槽和通孔结构。 超临界CO 2和第一甲硅烷基化剂用于形成化学键合的高密度表面层（160）。 使用超临界CO 2和第二甲硅烷化剂从低k电介质层（100）除去硅烷醇物质。 阻挡层（190）和铜（200）用于填充沟槽和通孔结构。

公开(公告)号：US06911394B2

公开(公告)日：2005-06-28

申请号：US10340932

申请日：2003-01-13

Applicant: Qing-Tang Jiang ,  Changming Jin ,  Joseph D. Luttmer

Inventor： Qing-Tang Jiang ,  Changming Jin ,  Joseph D. Luttmer

IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

CPC classification number: H01L21/76844 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76888

Abstract: A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectric layer (204) to expose a portion of the surface of the semiconductor substrate (202). The method also includes the step of forming a conductive layer (212, 220) within in the trench or the via (206). The method further includes the steps of polishing a portion of the conductive layer (220) and annealing the conductive layer (212, 220) at a predetermined temperature. Moreover, the conductive layer (212, 220) also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer (212, 220) to form a dopant oxide layer (212a, 220a) when the conductive layer (212, 220) is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供半导体衬底（202），在半导体衬底（202）上形成电介质层（204），以及蚀刻电介质层（204）中的沟槽或通孔（206） ）以暴露半导体衬底（202）的表面的一部分。 该方法还包括在沟槽或通孔（206）内形成导电层（212,220）的步骤。 该方法还包括以下步骤：抛光导电层（220）的一部分并在预定温度下退火导电层（212,220）。 此外，导电层（212,220）还包括掺杂剂，并且掺杂剂基本上扩散到导电层（212,220）的顶侧的表面，以形成掺杂剂氧化物层（212a，220a），当 导电层（212,220）在预定温度下退火，掺杂剂暴露于氧气。

公开(公告)号：US06573167B2

公开(公告)日：2003-06-03

申请号：US09921119

申请日：2001-08-02

Applicant: Guoqiang Xing ,  Wei-Yung Hsu ,  Changming Jin

Inventor： Guoqiang Xing ,  Wei-Yung Hsu ,  Changming Jin

IPC: H01L2122

CPC classification number: H01L21/0332 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32139 ,  H01L27/1085 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

Abstract: A carbon hardmask (122) for etching hard-to-etch materials (110/112/114) such as Pt, Ir, Ru, IrO2, RuO2, BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sputter etching using argon and limited or no oxygen may be used to etch the hard-to-etch materials (110/112/114) with high selectivity to the carbon hardmask (122).

公开(公告)号：US6059553A

公开(公告)日：2000-05-09

申请号：US992362

申请日：1997-12-17

Applicant: Changming Jin ,  Stacey Yamanaka ,  R. Scott List

Inventor： Changming Jin ,  Stacey Yamanaka ,  R. Scott List

IPC: C08G77/52 ,  H01L21/31 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  B05D3/02

CPC classification number: H01L21/02126 ,  H01L21/02203 ,  H01L21/02214 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/914 ,  Y10T428/12528

Abstract: An integrated circuit with an intermetal level dielectric (IMD) including an organic-silica hybrid (110) and located between metal lines (104).

Abstract translation: 一种具有包括有机二氧化硅杂化物（110）并位于金属线（104）之间的金属间电介质（IMD）的集成电路。

公开(公告)号：US20090160059A1

公开(公告)日：2009-06-25

申请号：US11961464

申请日：2007-12-20

Applicant: Ju-Ai Ruan ,  Sameer K. Ajmera ,  Changming Jin ,  Anand J. Reddy ,  Tae S. Kim

Inventor： Ju-Ai Ruan ,  Sameer K. Ajmera ,  Changming Jin ,  Anand J. Reddy ,  Tae S. Kim

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/53295 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).

Abstract translation: 本发明的一个方面提供一种形成半导体器件（100）的方法。 一个方面包括在半导体衬底（105）上形成晶体管（120,125），在晶体管（120,125）之上形成第一层间电介质层（165），并在第一层间电介质内形成金属互连（170,175） 层（165）。 使用含碳气体在沉积工具内的金属互连（170,175）和第一层间介电层（165）上形成氮化硅（SiCN）层（180）。 通过中断沉积室内的含碳气体的流动，在沉积工具内在SiCN层（180）上形成粘附层（185）。 第二层间介质层（190）形成在粘合层（185）上方。

公开(公告)号：US06583053B2

公开(公告)日：2003-06-24

申请号：US09816436

申请日：2001-03-23

Applicant: Jiong-Ping Lu ,  Changming Jin ,  David Permana

Inventor： Jiong-Ping Lu ,  Changming Jin ,  David Permana

IPC: H01L214763

CPC classification number: H01L21/76873 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7688

Abstract: A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108) is formed over the SiC layer (106). A trench (112) is etched in the sacrificial layer (108), the SiC layer (106) and the dielectric layer (102). A sputter etch of the sacrificial layer (108) is used to create a wider opening at a top of the sacrificial layer (108) than at a top of the dielectric layer (102). A barrier layer (114) and copper seed layer (116) are formed. The trench (112) is then filled with copper (124). CMP is used to remove the excess copper (124) and barrier layer (114) stopping on the SiC (106).

公开(公告)号：US07745335B2

公开(公告)日：2010-06-29

申请号：US11614511

申请日：2006-12-21

Applicant: Ju-Ai Ruan ,  Changming Jin ,  Sopa Chevacharoenkul ,  Satyavolu Papa Rao ,  Tae Seung Kim

Inventor： Ju-Ai Ruan ,  Changming Jin ,  Sopa Chevacharoenkul ,  Satyavolu Papa Rao ,  Tae Seung Kim

IPC: H01L21/4763 ,  H01L21/44 ,  B05D3/00

CPC classification number: H01L21/02074 ,  H01L21/76883 ,  Y10S438/937

Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

Abstract translation: 一种制造互连结构的方法，包括将空的沉积室暴露于在等离子体存在下产生由源气体产生的反应物质的方法。 该方法还包括终止等离子体，然后将其上的金属层的半导体衬底引入室中，同时反应物质存在于室中。