利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.022 秒)

    Method for forming polysilicon plug of semiconductor device
    3.
    发明授权
    Method for forming polysilicon plug of semiconductor device 有权
    用于形成半导体器件的多晶硅插塞的方法

    公开(公告)号：US07119015B2

    公开(公告)日：2006-10-10

    申请号：US10879220

    申请日：2004-06-30

    申请人： Hyung Soon Park ,  Min Suk Lee ,  Sang Ick Lee ,  Hyun Chul Sohn

    发明人： Hyung Soon Park ,  Min Suk Lee ,  Sang Ick Lee ,  Hyun Chul Sohn

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76897 ,  H01L21/7684

    摘要： Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.

    摘要翻译： 公开了一种用于形成半导体器件的多晶硅插塞的方法。 该方法包括以下步骤：在包括单元区域和外围电路区域的半导体衬底上形成字线和硬掩模膜的堆叠图案; 在所述堆叠图案的侧壁上形成间隔物; 在半导体衬底上形成层间绝缘膜; 通过使用硬掩模膜作为抛光阻挡膜的CMP工艺来研磨层间绝缘膜; 在包括层间绝缘膜的半导体衬底上形成阻挡膜; 选择性地蚀刻阻挡膜和层间绝缘膜以形成着陆塞接触孔; 在所述半导体衬底上沉积填充所述着地插头接触孔的多晶硅膜; 使用阻挡膜作为蚀刻阻挡膜对多晶硅膜进行绝缘蚀刻; 并使用硬掩模膜作为抛光阻挡膜研磨多晶硅膜和阻挡膜以形成多晶硅插塞。

    CMP slurry compositions for oxide films and methods for forming metal line contact plugs using the same
    4.
    发明授权
    CMP slurry compositions for oxide films and methods for forming metal line contact plugs using the same 失效
    用于氧化膜的CMP浆料组合物及使用其制备金属线接触塞的方法

    公开(公告)号：US07018924B2

    公开(公告)日：2006-03-28

    申请号：US10603976

    申请日：2003-06-25

    申请人： Jong Goo Jung ,  Sang Ick Lee

    发明人： Jong Goo Jung ,  Sang Ick Lee

    IPC分类号： H01L21/4763 ,  C09K13/04

    CPC分类号： C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684

    摘要： CMP slurries for oxide film and a method for forming a metal line contact plug of a semiconductor device are described herein. When a polishing process of a multi-layer film is performed by using the disclosed CMP slurry for oxide film including an HXOn compound (wherein n is an integer from 1 to 4), a stable landing plug poly can be formed by preventing step differences by reducing interlayer polishing speed differences.

    摘要翻译： 本文描述了用于氧化物膜的CMP浆料和用于形成半导体器件的金属线接触插塞的方法。 当通过使用所公开的包括HXO N n化合物（其中n是1至4的整数）的氧化物膜的CMP浆料进行多层膜的抛光工艺时，稳定的着色插塞聚 可以通过减少层间抛光速度差来防止台阶差来形成。

    Method for the formation of gate electrode of semiconductor device using a difference in polishing selection ratio between polymer and oxide film
    5.
    发明授权
    Method for the formation of gate electrode of semiconductor device using a difference in polishing selection ratio between polymer and oxide film 有权

    公开(公告)号：US06391697B2

    公开(公告)日：2002-05-21

    申请号：US09855849

    申请日：2001-05-16

    申请人： Sang-Ick Lee

    发明人： Sang-Ick Lee

    IPC分类号： H10L21336

    CPC分类号： H01L29/66545 ,  H01L21/3212 ,  H01L21/823437

    摘要： A method for the formation of a gate electrode with a uniform thickness in the semiconductor device by using a difference in polishing selection ratio between a polymer and an oxide film. The method includes steps of depositing a polymer layer on a semiconductor substrate; selectively etching the polymer layer to form a patterned polymer; forming an insulating oxide film for planarization; applying a CMP process to the insulating oxide film; removing the patterned polymer to define an opening with its bottom exposed to the substrate; forming a gate insulating film on the substrate within the opening; depositing an electrically conducting film to bury the opening; applying the CMP process to the electrically conducting film to allow it to remain only within the opening; removing a portion of the electrically conducting film formed within the opening by etching; depositing a mask nitride film to bury the top of the electrically conducting film; and applying the CMP process to the mask nitride film until the insulating oxide film is exposed.

    Slurry composition with high planarity and CMP process of dielectric film using the same
    7.
    发明授权
    Slurry composition with high planarity and CMP process of dielectric film using the same 失效
    具有高平坦度的浆料组合物和使用其的介电膜的CMP工艺

    公开(公告)号：US07271088B2

    公开(公告)日：2007-09-18

    申请号：US10999263

    申请日：2004-11-30

    申请人： Jong Goo Jung ,  Sang Ick Lee ,  Hyung Soon Park

    发明人： Jong Goo Jung ,  Sang Ick Lee ,  Hyung Soon Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76819 ,  C09G1/02 ,  H01L21/31053

    摘要： Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a molecular weight ranging from hundreds of thousands to millions, an abrasive, and water. A CMP process for polishing a dielectric film utilizes the disclosed slurry composition. The slurry composition enables complete and overall planarization of the dielectric film by polishing the part of the film having a higher step difference through CMP process. Accordingly, the disclosed slurry composition is useful for the CMP process of all semiconductor devices including those having ultrafine patterns.

    摘要翻译： 本文公开了具有高平面性的CMP浆料组合物和使用其的用于抛光电介质膜的CMP工艺。 更具体地说，具有高平面度的CMP浆料组合物包括具有数万个羧基并且分子量范围从数十万到数百万的碳化合物，研磨剂和水。 用于抛光电介质膜的CMP工艺利用所公开的浆料组合物。 浆料组合物通过CMP工艺研磨具有较高阶梯差的薄膜的部分，能够使电介质薄膜完全和全面平坦化。 因此，所公开的浆料组合物对于包括具有超细图案的半导体器件的所有半导体器件的CMP工艺是有用的。

    SUBSTRATE PROTECTING MEMBER AND METHOD OF FORMING ANALYSIS SAMPLE USING THE SAME
    10.
    发明申请
    SUBSTRATE PROTECTING MEMBER AND METHOD OF FORMING ANALYSIS SAMPLE USING THE SAME 审中-公开
    基板保护构件及使用其形成分析样品的方法

    公开(公告)号：US20070152168A1

    公开(公告)日：2007-07-05

    申请号：US11617159

    申请日：2006-12-28

    申请人： Taek-Jin Lim ,  Jin-Sung Kim ,  Sang-Ick Lee

    发明人： Taek-Jin Lim ,  Jin-Sung Kim ,  Sang-Ick Lee

    IPC分类号： G21G5/00

    CPC分类号： G01N1/32 ,  G01N1/286

    摘要： In a substrate protecting member and a method of forming an analysis sample using the same, the substrate protecting member includes a protective layer attached to a semiconductor substrate to protect a defect portion of the semiconductor substrate and a sensing line including first, second and third conductive lines located on the protective layer. The first conductive line extends in a first direction. The second conductive line extends to an edge of the protective layer in a second direction different from the first direction. The second and third conductive lines are electrically connected to first and second end portions of the first conductive line, respectively. The third conductive line extends to an edge of the protective layer in the second direction.

    摘要翻译： 在基板保护部件和使用其的分析用样品的形成方法中，基板保护部件包括附着于半导体基板的保护层，以保护半导体基板的缺陷部分，以及包括第一，第二和第三导电 位于保护层上的线。 第一导线沿第一方向延伸。 第二导线沿与第一方向不同的第二方向延伸到保护层的边缘。 第二和第三导线分别电连接到第一导电线的第一和第二端部。 第三导线在第二方向延伸到保护层的边缘。