公开(公告)号：US06984586B2

公开(公告)日：2006-01-10

申请号：US10318017

申请日：2002-12-13

申请人： Noriki Iwasaki ,  Satoru Fukunaga ,  Tadayuki Into

发明人： Noriki Iwasaki ,  Satoru Fukunaga ,  Tadayuki Into

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/6835 ,  B24B37/30 ,  B24B41/068 ,  H01L21/30625 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834

摘要： In a method of thinning a semiconductor wafer, a protection tape smaller in size than the semiconductor wafer is applied to a front of the semiconductor wafer, and a back of the semiconductor wafer is etched. In the etching process, a chemical liquid falls down from the semiconductor wafer without being accumulated on the protection tape because the protection tape is smaller in size than the semiconductor wafer.

公开(公告)号：US06520844B2

公开(公告)日：2003-02-18

申请号：US09866704

申请日：2001-05-30

申请人： Noriki Iwasaki ,  Satoru Fukunaga ,  Tadayuki Into

发明人： Noriki Iwasaki ,  Satoru Fukunaga ,  Tadayuki Into

IPC分类号： B24B500

CPC分类号： H01L21/6835 ,  B24B37/30 ,  B24B41/068 ,  H01L21/30625 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834

摘要： In a method of thinning a semiconductor wafer, a protection tape smaller in size than the semiconductor wafer is applied to a front of the semiconductor wafer, and a back of the semiconductor wafer is etched. In the etching process, a chemical liquid falls down from the semiconductor wafer without being accumulated on the protection tape because the protection tape is smaller in size than the semiconductor wafer.

公开(公告)号：US5247248A

公开(公告)日：1993-09-21

申请号：US832696

申请日：1992-02-07

申请人： Satoru Fukunaga

发明人： Satoru Fukunaga

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H05K1/14 ,  H05K3/32

CPC分类号： G01R31/2863 ,  G01R31/2862 ,  H05K1/14 ,  H05K3/325

摘要： In order to improve the operability of a burn-in apparatus, to shorten the operating time, to reduce the number of the components, and to increase the package density of semiconductor integrated circuits to be accommodated within a burn-in apparatus, semiconductor integrated circuits with a lead frame are mounted on a first wiring board by means of fixing the pressuring member to the first wiring board with a magnetic force. Thereafter, the first wiring board is mounted to a second wiring board, and both are to be inserted into a burn-in apparatus.

摘要翻译： 为了提高老化装置的可操作性，为了缩短操作时间，减少部件数量，并且增加要容纳在老化装置内的半导体集成电路的封装密度，半导体集成电路 通过利用磁力将加压构件固定在第一配线基板上，引线框安装在第一布线板上。 此后，将第一布线板安装到第二布线板上，并将它们都插入老化装置。

公开(公告)号：US5412314A

公开(公告)日：1995-05-02

申请号：US6306

申请日：1993-01-22

申请人： Satoru Fukunaga ,  Junichirou Hisatomi ,  Kazuhiro Nakamura ,  Ken'ichi Ohi ,  Hideki Tanaka ,  Masayuki Tabuchi

发明人： Satoru Fukunaga ,  Junichirou Hisatomi ,  Kazuhiro Nakamura ,  Ken'ichi Ohi ,  Hideki Tanaka ,  Masayuki Tabuchi

IPC分类号： G01R31/00 ,  G01R31/01 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66

CPC分类号： G01R31/2893 ,  G01R31/2851 ,  G01R31/01

摘要： A package tester includes an inlet station for arranging a test board in which package sockets mounting packages are disposed in one or plural lines for performing package test by flowing an electric current through the package and transmitting signals to the package, the package being composed of parts including electric parts or electronic parts and being sequentially formed on a package tape, an inlet pusher for pushing the test board mounting the packages by a width of the test board in a feeding direction of the test board from the inlet station to the package socket, a conveyor for receiving the test board sequentially pushed out of the inlet station by the inlet pusher and conveying the received test board to a testing area, a contact device opposed to the conveyor and capable of being electrically connected to the test board arranged on the conveyor, an outlet station receiving the test board sequentially pushed out of the conveyor by sequentially pushing-out of the test board by means of the inlet pusher, and a reaction urging device for allowing the test board to be pushed out while supporting the test board pushed out to the outlet station with force weaker than pushing out force in the inlet pusher.

摘要翻译： 包装测试器包括用于布置测试板的入口站，其中包装插座安装封装设置在一行或多行中，用于通过使电流流过封装并将信号传输到封装件来进行封装测试，封装由部件 包括电气部件或电子部件，并且顺序地形成在封装带上;入口推动器，用于将测试板沿着测试板的馈送方向从入口站到封装插座将测试板的宽度安装在测试板的宽度上， 输送机，用于通过入口推动器顺序地从进样台推出测试板，并将接收到的测试板传送到测试区域，与传送器相对的接触装置，并且能够电连接到布置在输送机上的测试板 通过顺次推出测试板，接收测试板的出口站顺序地从输送机中推出 通过入口推动器，以及反作用力装置，用于允许测试板被推出，同时以比推入入口推动器中的推力更弱的力将支撑被推出到出口台的测试板。

公开(公告)号：US06423102B1

公开(公告)日：2002-07-23

申请号：US08987054

申请日：1997-12-09

申请人： Satoru Fukunaga ,  Hiroyuki Nakanishi

发明人： Satoru Fukunaga ,  Hiroyuki Nakanishi

IPC分类号： H01L2100

CPC分类号： B25B11/005 ,  H01L21/6835 ,  H01L24/78 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/78 ,  H01L2224/78301 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/14 ,  Y10S277/91 ,  Y10T29/41 ,  H01L2224/45099 ,  H01L2924/00

摘要： A jig used for assembling semiconductor devices has an arrangement wherein the first semiconductor integrated circuit chip, which is die-bonded and wire-bonded onto one surface of a lead frame, is fitted to the inner section of a support stage and is supported by an elastic member that is designed to be higher than the inner section, while the lead frame is supported by the outer section of the support stage. In this state, the second semiconductor integrated circuit chip is die-bonded onto the other surface of the lead frame by applying pressure by means of a bonding collet. Thus, it becomes possible to prevent cracks that may be caused in a passivation film and also to improve the reliability and the final yield of semiconductor devices.

摘要翻译： 用于组装半导体器件的夹具具有以下结构：其中芯片接合并引线接合到引线框架的一个表面上的第一半导体集成电路芯片被安装到支撑台的内部并由 弹性构件被设计成高于内部部分，而引线框架由支撑台的外部部分支撑。 在这种状态下，第二半导体集成电路芯片通过使用粘合夹头施加压力而被芯片接合到引线框架的另一个表面上。 因此，可以防止钝化膜中可能引起的裂纹，并且还可以提高半导体器件的可靠性和最终产量。