公开(公告)号：US20190066799A1

公开(公告)日：2019-02-28

申请号：US15691584

申请日：2017-08-30

Applicant: Ting Luo ,  Kulachet Tanpairoj ,  Harish Singidi ,  Jianmin Huang ,  Preston Thomson ,  Sebastien Andre Jean

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Singidi ,  Jianmin Huang ,  Preston Thomson ,  Sebastien Andre Jean

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3409 ,  G11C16/3445 ,  H01L27/11556 ,  H01L27/11582

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US20180364918A1

公开(公告)日：2018-12-20

申请号：US16012728

申请日：2018-06-19

Applicant: Sebastien Andre Jean

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including identifying inactive data in a group of volatile memory cells of a host device, assembling identified inactive data in an offload unit of the group of volatile memory cells, and writing the offload unit of inactive data to a group of non-volatile memory cells of a storage system when the amount of inactive data in the offload unit reaches a threshold.

公开(公告)号：US20190065080A1

公开(公告)日：2019-02-28

申请号：US15690869

申请日：2017-08-30

Applicant: Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Jianmin Huang

Inventor： Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F3/06 ,  G06F12/0811

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

公开(公告)号：US20190013081A1

公开(公告)日：2019-01-10

申请号：US16023926

申请日：2018-06-29

Applicant: Greg A. Blodgett ,  Sebastien Andre Jean

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3418 ,  G06F1/3206 ,  G06F12/1408 ,  G06F12/1441 ,  G11C7/04 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2213/71

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

公开(公告)号：US20190013079A1

公开(公告)日：2019-01-10

申请号：US16023386

申请日：2018-06-29

Applicant: Greg A. Blodgett ,  Sebastien Andre Jean

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Apparatus and methods are disclosed including a memory device or a memory controller configured to receive, from a host device over a host interface, a request for a device descriptor of a memory device, and to send to the host, over the host interface, the device descriptor, the device descriptor including voltage supply capability fields that are set to indicate supported voltages of the memory device, the supported voltages selected from a plurality of discrete voltages. The host device can utilize the supported voltages to supply an appropriate voltage to the memory device. Methods of operation are disclosed, as well as machine-readable medium, a host computing device, and other embodiments.

公开(公告)号：US20180364947A1

公开(公告)日：2018-12-20

申请号：US16012750

申请日：2018-06-19

Applicant: Sebastien Andre Jean

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0649 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/068 ,  G11C16/0483 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

公开(公告)号：US20180364939A1

公开(公告)日：2018-12-20

申请号：US16012736

申请日：2018-06-19

Applicant: Sebastien Andre Jean

Inventor： Sebastien Andre Jean

IPC: G06F3/06

Abstract: Apparatus and methods are disclosed, including identifying and tagging data in a group of volatile memory cells of a host device to be written to and maintained contiguously on non-volatile memory of a storage system, and writing the tagged data to the group of non-volatile memory cells. A host device includes a host processor and the group of volatile memory cells, and a storage system includes the group of non-volatile memory cells.