公开(公告)号：US20180336950A1

公开(公告)日：2018-11-22

申请号：US16040837

申请日：2018-07-20

申请人： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

发明人： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

IPC分类号： G11C16/04 ,  G11C5/02 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  G11C5/06

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US10482964B2

公开(公告)日：2019-11-19

申请号：US16040837

申请日：2018-07-20

申请人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

发明人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

IPC分类号： G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H01L49/02

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US10049744B2

公开(公告)日：2018-08-14

申请号：US15383213

申请日：2016-12-19

申请人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

发明人： Da Woon Jeong ,  Sung-Hun Lee ,  Seokjung Yun ,  Hyunmog Park ,  JoongShik Shin ,  Young-Bae Yoon

IPC分类号： H01L29/788 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US20190148295A1

公开(公告)日：2019-05-16

申请号：US16247712

申请日：2019-01-15

申请人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

发明人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC分类号： H01L23/528 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11578 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11556

摘要： A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US20170200676A1

公开(公告)日：2017-07-13

申请号：US15383213

申请日：2016-12-19

申请人： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

发明人： Da Woon JEONG ,  Sung-Hun LEE ,  Seokjung YUN ,  Hyunmog PARK ,  JoongShik SHIN ,  Young-Bae YOON

IPC分类号： H01L23/528 ,  H01L27/11556 ,  H01L27/1157 ,  G11C16/04 ,  H01L23/522 ,  H01L21/768 ,  G11C16/08 ,  H01L27/11524 ,  H01L27/11582

CPC分类号： G11C16/0483 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/00

摘要： Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

公开(公告)号：US20170179028A1

公开(公告)日：2017-06-22

申请号：US15350305

申请日：2016-11-14

申请人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

发明人： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.