公开(公告)号：US20180053775A1

公开(公告)日：2018-02-22

申请号：US15466111

申请日：2017-03-22

Applicant: Phil Ouk Nam ,  Hyung Joon Kim ,  Sung Gil Kim ,  Ji Hoon Choi ,  Seulye Kim ,  Hong Suk Kim ,  Jae Young Ahn

Inventor： Phil Ouk Nam ,  Hyung Joon Kim ,  Sung Gil Kim ,  Ji Hoon Choi ,  Seulye Kim ,  Hong Suk Kim ,  Jae Young Ahn

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/402 ,  H01L29/408

Abstract: A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.

公开(公告)号：US20180108672A1

公开(公告)日：2018-04-19

申请号：US15484339

申请日：2017-04-11

Applicant: Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US09953999B2

公开(公告)日：2018-04-24

申请号：US15375944

申请日：2016-12-12

Applicant: Phil Ouk Nam ,  Sung Gil Kim ,  Seulye Kim ,  Hong Suk Kim ,  Jae Young Ahn ,  Ji Hoon Choi

Inventor： Phil Ouk Nam ,  Sung Gil Kim ,  Seulye Kim ,  Hong Suk Kim ,  Jae Young Ahn ,  Ji Hoon Choi

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42324 ,  H01L29/4234

Abstract: In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.

公开(公告)号：US09831267B2

公开(公告)日：2017-11-28

申请号：US15239434

申请日：2016-08-17

Applicant: Seulye Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jung Ho Kim ,  Jintae Noh ,  Eun-Young Lee

Inventor： Seulye Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jung Ho Kim ,  Jintae Noh ,  Eun-Young Lee

IPC: H01L27/115 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/76831 ,  H01L23/485 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a plurality of vertical structures penetrating the stack structures, a common source plug between the stack structures that are adjacent to each other and extending in parallel to the stack structures, and a spacer structure at each side of the common source plug. The stack structure has a sidewall defining recess regions vertically spaced apart from each other. The spacer structure covers sidewalls of the stack structures. The spacer structure includes an insulating spacer and a protection spacer. The insulating spacer fills the recess regions of the stack structure and includes a surface having grooves. The protection spacer fills the grooves of the surface of the insulating spacer and has a substantially flat surface.

公开(公告)号：US10002875B2

公开(公告)日：2018-06-19

申请号：US15466111

申请日：2017-03-22

Applicant: Phil Ouk Nam ,  Hyung Joon Kim ,  Sung Gil Kim ,  Ji Hoon Choi ,  Seulye Kim ,  Hong Suk Kim ,  Jae Young Ahn

Inventor： Phil Ouk Nam ,  Hyung Joon Kim ,  Sung Gil Kim ,  Ji Hoon Choi ,  Seulye Kim ,  Hong Suk Kim ,  Jae Young Ahn

IPC: H01L29/49 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/402 ,  H01L29/408

Abstract: A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.

公开(公告)号：US20180026046A1

公开(公告)日：2018-01-25

申请号：US15375944

申请日：2016-12-12

Applicant: Phil Ouk NAM ,  Sung Gil KIM ,  Seulye KIM ,  Hong Suk KIM ,  Jae Young AHN ,  Ji Hoon CHOI

Inventor： Phil Ouk NAM ,  Sung Gil KIM ,  Seulye KIM ,  Hong Suk KIM ,  Jae Young AHN ,  Ji Hoon CHOI

IPC: H01L27/11582 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42324 ,  H01L29/4234

Abstract: In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.

公开(公告)号：US20170084626A1

公开(公告)日：2017-03-23

申请号：US15239434

申请日：2016-08-17

Applicant: Seulye Kim ,  Ji-Hoon CHOI ,  Dongkyum KIM ,  Jung Ho KIM ,  Jintae NOH ,  Eun-Young LEE

Inventor： Seulye Kim ,  Ji-Hoon CHOI ,  Dongkyum KIM ,  Jung Ho KIM ,  Jintae NOH ,  Eun-Young LEE

IPC: H01L27/115 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76831 ,  H01L23/485 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a plurality of vertical structures penetrating the stack structures, a common source plug between the stack structures that are adjacent to each other and extending in parallel to the stack structures, and a spacer structure at each side of the common source plug. The stack structure has a sidewall defining recess regions vertically spaced apart from each other. The spacer structure covers sidewalls of the stack structures. The spacer structure includes an insulating spacer and a protection spacer. The insulating spacer fills the recess regions of the stack structure and includes a surface having grooves. The protection spacer fills the grooves of the surface of the insulating spacer and has a substantially flat surface.

公开(公告)号：US20170033044A1

公开(公告)日：2017-02-02

申请号：US15160137

申请日：2016-05-20

Applicant: Ji-Hoon CHOI ,  Jung Ho KIM ,  Dongkyum KIM ,  Seulye KIM ,  Jintae NOH ,  Hyun-Jin SHIN ,  SeungHyun LIM

Inventor： Ji-Hoon CHOI ,  Jung Ho KIM ,  Dongkyum KIM ,  Seulye KIM ,  Jintae NOH ,  Hyun-Jin SHIN ,  SeungHyun LIM

IPC: H01L23/522 ,  G11C8/10 ,  H01L23/532 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.

Abstract translation: 提供半导体器件。 半导体器件包括堆叠结构，其包括交替堆叠在衬底上的绝缘图案和电极结构以及垂直穿过堆叠结构的垂直沟道结构。 每个电极结构包括具有第一侧壁和与第一侧壁相对的第二侧壁的导电图案，第一侧壁上的第一蚀刻防止图案和第二侧壁上的第二蚀刻防止图案。