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    Max-flow/min-cut solution algorithm for early terminating push-relabel algorithm
    1.
    发明授权
    Max-flow/min-cut solution algorithm for early terminating push-relabel algorithm 有权

    公开(公告)号：US12223691B2

    公开(公告)日：2025-02-11

    申请号：US17798898

    申请日：2021-09-22

    Applicant: SHANGHAITECH UNIVERSITY

    Inventor： Xinzhe Liu ,  Guangyao Yan ,  Yajun Ha

    IPC: G06V10/762 ,  G06V10/764 ,  G06V10/96

    Abstract: A max-flow/min-cut solution algorithm for early terminating a push-relabel algorithm is provided. The max-flow/min-cut solution algorithm is used for an application that does not require an exact maximum flow, and includes: defining an early termination condition of the push-relabel algorithm by a separation condition and a stable condition; determining that the separation condition is satisfied if there is no source node s, s∈S, in the set T at any time in an operation process of the push-relabel algorithm; determining that the stable condition is satisfied if there is no active node in the set T; and terminating the push-relabel algorithm if both the separation condition and the stability condition are satisfied. The early termination technique is proposed to greatly reduce redundant computations and ensure that the algorithm terminates correctly in all cases.

    Method for catalytic synthesis of ammonia under normal pressures
    2.
    发明授权
    Method for catalytic synthesis of ammonia under normal pressures 有权

    公开(公告)号：US12129179B2

    公开(公告)日：2024-10-29

    申请号：US18034382

    申请日：2021-11-19

    Applicant: ShanghaiTech University

    Inventor： Xiaofei Guan ,  Zujian Tang

    IPC: B01J23/14 ,  B01J23/04 ,  B01J35/61 ,  C01C1/04

    CPC classification number: C01C1/0411 ,  B01J23/04 ,  B01J23/14 ,  B01J35/618 ,  C01C1/0482

    Abstract: A method for catalytic synthesis of ammonia under normal pressures, including: performing a reaction of hydrogen and nitrogen to synthesize ammonia under normal pressures by taking a liquid alloy as a catalyst in a reactor, where the reactor contains a molten salt, the density of the molten salt is smaller than that of the liquid alloy, and the molten salt is used for providing a reaction interface and isolating the liquid alloy from being introduced impurities. The first metal reacts with the nitrogen to produce the metal nitride, and the molten salt provides a new reaction interface for the metal nitride to react with the hydrogen to synthesize ammonia, so that ammonia is produced continuously. In addition, the molten salt prevents the liquid alloy from contacting with the oxygen and the water vapor, which prevents the liquid alloy from being oxidized, thus prolonging its service life.

    Mixed-precision Neural Network Systems
    3.
    发明公开
    Mixed-precision Neural Network Systems 审中-公开

    公开(公告)号：US20240296308A1

    公开(公告)日：2024-09-05

    申请号：US18646852

    申请日：2024-04-26

    Applicant: SHANGHAITECH UNIVERSITY

    Inventor： Yueyang ZHENG ,  Chaolin RAO ,  Minye WU ,  Xin LOU ,  Pingqiang ZHOU ,  Jingyi YU

    IPC: G06N3/04

    CPC classification number: G06N3/04

    Abstract: A computing system for encoding a machine learning model comprises a plurality of layers and a plurality of computation units. A first set of computation units are configured to process data at a first bit width. A second set of computation units are configured to process at a second bit width. The first bit width is higher than the second bit width. A memory is coupled to the computation units. A controller is coupled to the computation units and the memory. The controller is configured to provide instructions for encoding the machine learning model. The first set of computation units are configured to compute a first set of layers and the second set of computation units are configured to compute a second set of layers.

    ENERGY-EFFICIENT CRYOGENIC-IN-MEMORY-COMPUTING (CIMC) ACCELERATOR
    6.
    发明公开
    ENERGY-EFFICIENT CRYOGENIC-IN-MEMORY-COMPUTING (CIMC) ACCELERATOR 审中-公开

    公开(公告)号：US20240221811A1

    公开(公告)日：2024-07-04

    申请号：US18229698

    申请日：2023-08-03

    Applicant: SHANGHAITECH UNIVERSITY

    Inventor： Yuhao SHU ,  Hongtu ZHANG ,  Yajun HA

    IPC: G11C11/405 ,  G06F17/15 ,  G11C11/4091 ,  G11C11/4096 ,  H03K19/20

    CPC classification number: G11C11/405 ,  G06F17/153 ,  G11C11/4091 ,  G11C11/4096 ,  H03K19/20

    Abstract: An energy-efficient cryogenic-in-memory-computing (CIMC) accelerator includes cryogenic 3T (C3T) macros. Each of the C3T macros comprises a C3T array containing M rows×N columns of bitcells. An input signal is converted into a timing sequence signal of a corresponding pulse width by using a digital timing sequence converter array. A C3T bitcell of a corresponding row in the C3T macro is controlled to perform charging and discharging on a read bit line (RBL) of a corresponding column. A voltage on the RBL of the corresponding column is sampled by a sense amplifier configured in each C3T macro to obtain a final result. With adaptive reference voltage configuration and storage on the chip, this design can achieve fast and low-power boolean/convolutional computing.

    ULTRA-LOW-VOLTAGE STATIC RANDOM ACCESS MEMORY (SRAM) CELL FOR ELIMINATING HALF-SELECT DISTURBANCE UNDER BIT INTERLEAVING STRUCTURE
    7.
    发明公开
    ULTRA-LOW-VOLTAGE STATIC RANDOM ACCESS MEMORY (SRAM) CELL FOR ELIMINATING HALF-SELECT DISTURBANCE UNDER BIT INTERLEAVING STRUCTURE 审中-公开

    公开(公告)号：US20240212748A1

    公开(公告)日：2024-06-27

    申请号：US18233350

    申请日：2023-08-14

    Applicant: SHANGHAITECH UNIVERSITY

    Inventor： Yifei LI ,  Jian CHEN ,  Yajun HA ,  Hongyu CHEN

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4, where the two N-type transistors NM3 and NM4 form a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.

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