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    Memory access system including support for multiple bus widths
    2.
    发明授权
    Memory access system including support for multiple bus widths 有权
    存储器访问系统包括支持多个总线宽度

    公开(公告)号：US07281066B2

    公开(公告)日：2007-10-09

    申请号：US11221265

    申请日：2005-09-07

    申请人： Sheila M. Rader ,  Pradeep Garani ,  Franz Steininger ,  Brian G. Lucas

    发明人： Sheila M. Rader ,  Pradeep Garani ,  Franz Steininger ,  Brian G. Lucas

    IPC分类号： G06F3/00

    CPC分类号： E04F21/28 ,  B29C63/02 ,  B29L2031/005 ,  B65H35/0013 ,  B65H2701/3772 ,  E04F21/1657 ,  G06F13/385 ,  G06F2213/3814 ,  Y02D10/14 ,  Y02D10/151 ,  Y10T156/1084 ,  Y10T156/1343

    摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

    摘要翻译： 直接存储器存取系统由建立直接存储器访问数据通道的直接存储器访问控制器组成，并且包括用于耦合到存储器的第一接口。 第二接口用于耦合到多个节点。 并且处理器耦合到直接存储器访问控制器并且耦合到第二接口，其中处理器配置直接存储器访问数据信道以在可编程选择的多个节点中的一个或多个节点和存储器之间传送数据。 在一些实施例中，多个节点是要在无线多媒体手持电话中实现的多媒体处理器平台的数字信号处理器存储器和主处理器存储器。

    Shared memory architecture
    3.
    发明授权
    Shared memory architecture 有权

    公开(公告)号：US07127563B2

    公开(公告)日：2006-10-24

    申请号：US11220735

    申请日：2005-09-07

    申请人： Sheila M. Rader

    发明人： Sheila M. Rader

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1684

    摘要： A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

    Integrated processor platform supporting wireless handheld multi-media devices
    5.
    发明授权
    Integrated processor platform supporting wireless handheld multi-media devices 有权
    支持无线手持多媒体设备的集成处理器平台

    公开(公告)号：US07089344B1

    公开(公告)日：2006-08-08

    申请号：US09591682

    申请日：2000-06-09

    申请人： Sheila M. Rader ,  Pradeep Garani ,  Franz Steininger ,  Brian G. Lucas

    发明人： Sheila M. Rader ,  Pradeep Garani ,  Franz Steininger ,  Brian G. Lucas

    IPC分类号： G06F13/28

    CPC分类号： G06F13/387 ,  G06F2213/3814 ,  Y02D10/14 ,  Y02D10/151

    摘要： A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second interface is for coupling to a plurality of nodes. And a processor is coupled to the direct memory access controller and coupled to the second interface, wherein the processor configures the direct memory access data channel to transfer data between a programmably selectable respective one or more of the plurality of nodes and the memory. In some embodiments, the plurality of nodes are a digital signal processor memory and a host processor memory of a multi-media processor platform to be implemented in a wireless multi-media handheld telephone.

    摘要翻译： 直接存储器存取系统由建立直接存储器访问数据通道的直接存储器访问控制器组成，并且包括用于耦合到存储器的第一接口。 第二接口用于耦合到多个节点。 并且处理器耦合到直接存储器访问控制器并且耦合到第二接口，其中处理器配置直接存储器访问数据信道以在可编程选择的多个节点中的一个或多个节点和存储器之间传送数据。 在一些实施例中，多个节点是要在无线多媒体手持电话中实现的多媒体处理器平台的数字信号处理器存储器和主处理器存储器。

    Mobile wireless communication device architectures and methods therefor
    6.
    发明授权
    Mobile wireless communication device architectures and methods therefor 有权
    移动无线通信设备的架构及方法

    公开(公告)号：US06950910B2

    公开(公告)日：2005-09-27

    申请号：US10008939

    申请日：2001-11-08

    申请人： Sheila M. Rader

    发明人： Sheila M. Rader

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/16

    CPC分类号： G06F13/1684

    摘要： A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

    摘要翻译： 一种具有通过对应的第一和第二数据总线耦合到虚拟通道存储器控制器的第一和第二同步存储器件的无线通信架构，以及互连虚拟通道存储器控制器与第一和第二同步存储器件的共享地址和控制总线。 第一和第二同步存储器设备用共享地址总线寻址，并且第一和第二存储器位置分别经由第一和第二数据总线被访问。

    Apparatus for infrared channel and method therefor
    7.
    发明授权
    Apparatus for infrared channel and method therefor 失效
    红外线通道装置及其方法

    公开(公告)号：US5907418A

    公开(公告)日：1999-05-25

    申请号：US513037

    申请日：1995-08-09

    申请人： Thomas J. Walczak ,  Rachid Alameh ,  Sheila M. Rader

    发明人： Thomas J. Walczak ,  Rachid Alameh ,  Sheila M. Rader

    IPC分类号： G06F3/00 ,  G06F13/00 ,  H04B7/26 ,  H04B10/02 ,  H04B10/10 ,  H04B10/105 ,  H04B10/18 ,  H04B10/22 ,  H04M1/725 ,  H04M1/73 ,  H04B10/00

    CPC分类号： H04M1/7253 ,  H04B10/1143 ,  H04W52/0238 ,  H04W52/0258

    摘要： An infrared channel includes an IR transmitter circuit (302) and an IR receiver circuit (304). The transmitter circuit encodes data packets (400) which include a precursor segment, a synchronization segment, and a data field, the data field including data words, which words are bytes of data encoded by adding ones complement data bits and interleaving data subfields. The data fields are for infrared emission by the light source. A receiver circuit processor (316 or 508) is coupled to input samples to detect the presence of a precursor during a predetermined time period, and sleeping for a time interval, between inputting samples, which is substantially longer than the predetermined time period. The transmitter circuit transmits the precursor for a period of time at least as long as the sleep interval.

    摘要翻译： 红外线通道包括IR发送器电路（302）和IR接收器电路（304）。 发射机电路对包括前兆段，同步段和数据字段的数据分组（400）进行编码，数据字段包括数据字，哪些字是通过加1个补码数据位和交织数据子字段编码的数据字节。 数据字段用于光源的红外发射。 接收器电路处理器（316或508）耦合到输入样本以在预定时间段期间检测前体的存在，并且在输入样本之间的时间间隔睡眠，其基本上长于预定时间段。 发射机电路将前体传输至少与睡眠间隔一样长的时间段。

    Display system and circuit therefor
    8.
    发明授权
    Display system and circuit therefor 失效
    显示系统及其电路

    公开(公告)号：US5867140A

    公开(公告)日：1999-02-02

    申请号：US758019

    申请日：1996-11-27

    申请人： Sheila M. Rader

    发明人： Sheila M. Rader

    IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/36 ,  H04M1/02 ,  H04M1/73 ,  G09G5/00

    CPC分类号： G09G5/363 ,  H04M1/0214 ,  H04M1/0245 ,  H04W52/027 ,  G09G2330/021 ,  G09G2330/022 ,  Y02B60/50

    摘要： A display system includes a display panel (200) having a full display screen area (303) upon which images can be generated for viewing. An image control circuit (400, 501) controls the operation of the display panel such that only a partial display field, or area, (305) is controlled to generate images in a first operating mode to conserve power and the full display screen area is controlled to generate images in a second operating mode.

    摘要翻译： 显示系统包括具有完全显示屏幕区域（303）的显示面板（200），在该显示屏区域上可以生成用于观看的图像。 图像控制电路（400,501）控制显示面板的操作，使得仅控制部分显示区域（305）以在第一操作模式中生成图像以节省功率，并且全屏显示区域 被控制以在第二操作模式下生成图像。