公开(公告)号：US06919253B2

公开(公告)日：2005-07-19

申请号：US10359553

申请日：2003-02-07

申请人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

发明人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

摘要翻译： 根据本发明的制造半导体器件的方法包括步骤A，其在衬底的表面上形成多晶或无定形初级半导体层以具有开口部分和在同时形成外延生长层的步骤B上 通过开口部分的衬底的暴露部分和初步半导体层上的非外延生长层，使用CVD方法，同时通过反应室内的热源在反应室内加热衬底，外延 生长层由单晶半导体制成，非外延生长层由多晶或非晶半导体层组成。

公开(公告)号：US20050066887A1

公开(公告)日：2005-03-31

申请号：US10359553

申请日：2003-02-07

申请人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

发明人： Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Shigetaka Aoki

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L29/739 ,  H01L31/0336

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

摘要： A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.

摘要翻译： 根据本发明的制造半导体器件的方法包括步骤A，其在衬底的表面上形成多晶或无定形初级半导体层以具有开口部分和在同时形成外延生长层的步骤B上 通过开口部分的衬底的暴露部分和初步半导体层上的非外延生长层，使用CVD方法，同时通过反应室内的热源在反应室内加热衬底，外延 生长层由单晶半导体制成，非外延生长层由多晶或非晶半导体层组成。

公开(公告)号：US20090321880A1

公开(公告)日：2009-12-31

申请号：US12391939

申请日：2009-02-24

申请人： Shigetaka Aoki

发明人： Shigetaka Aoki

IPC分类号： H01L29/72

CPC分类号： H01L29/7371 ,  H01L29/1004 ,  H01L29/66242

摘要： A semicoductor device includes: a collector layer made of a first conductivity type semiconductor; an intrinsic base layer formed on the collector layer and including a second conductivity type monocrystalline silicon germanium layer; a base extraction electrode formed around the intrinsic base layer and including a second conductivity type polycrystalline silicon layer and a second conductivity type polycrystalline silicon germanium layer; and a first conductivity type emitter layer formed in an upper portion of the intrinsic base layer. A silicon layer is formed in the upper portion of the intrinsic base layer and the emitter layer includes an upper emitter region formed in an upper portion of the silicon layer and a lower emitter region formed below and in contact with the upper emitter region.

摘要翻译： 半导体器件包括：由第一导电类型半导体制成的集电极层; 形成在集电极层上并包括第二导电型单晶硅锗层的本征基极层; 基本提取电极，形成在本征基极层周围并且包括第二导电型多晶硅层和第二导电型多晶硅锗层; 以及形成在本征基极层的上部的第一导电型发射极层。 在本征基极层的上部形成有硅层，发射极层包括形成在硅层的上部的上部发射极区域和形成于下部并与上部发射极区域接触的下部发射极区域。

公开(公告)号：US20080230808A1

公开(公告)日：2008-09-25

申请号：US11970089

申请日：2008-01-07

申请人： Shigetaka Aoki

发明人： Shigetaka Aoki

IPC分类号： H01L29/737

CPC分类号： H01L29/7371 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7378

摘要： A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.

摘要翻译： 由SiGe混晶构成的基层包括与集电体层接触形成的间隔层，其中没有扩散基底杂质，并且本征基极层与其中扩散有碱性杂质的发射极层形成接触。 间隔层含有低浓度的C。 本征基层具有在集电极侧含有低浓度C的第一区域和在发射极侧含有高浓度C的第二区域。

公开(公告)号：US07859030B2

公开(公告)日：2010-12-28

申请号：US11706338

申请日：2007-02-15

申请人： Shigetaka Aoki

发明人： Shigetaka Aoki

IPC分类号： H01L29/66

CPC分类号： H01L29/1004 ,  H01L29/66242 ,  H01L29/7378

摘要： A SiGe-HBT having a base region made of SiGe mixed crystal. The base region includes: an intrinsic base region having junctions with a collector region and an emitter region; and an external base region for connecting the intrinsic base region with a base electrode. The intrinsic base region and the external base region are doped with a first impurity of a given conductivity type. The external base region is further doped with a second impurity. As the first impurity, an element smaller in atomic radius than Si (such as boron, for example) is selected, and as the second impurity, an element larger in atomic radius than the first impurity (such as Ge, In and Ga, for example) is selected.

摘要翻译： 具有由SiGe混合晶体制成的基极区域的SiGe-HBT。 基极区域包括：具有与集电极区域和发射极区域接合的本征基极区域; 以及用于将本征基极区域与基极电极连接的外部基极区域。 本征基极区域和外部基极区域掺杂有给定导电类型的第一杂质。 外部基极区域进一步掺杂有第二杂质。 作为第一杂质，选择原子半径小于Si（例如硼）的元素，作为第二杂质，原子半径比第一杂质大（例如Ge，In和Ga，对于 示例）。

公开(公告)号：US07109095B2

公开(公告)日：2006-09-19

申请号：US10396505

申请日：2003-03-26

申请人： Hidenori Notake ,  Teruhito Ohnishi ,  Akira Asai ,  Shigetaka Aoki

发明人： Hidenori Notake ,  Teruhito Ohnishi ,  Akira Asai ,  Shigetaka Aoki

IPC分类号： H01L21/20

CPC分类号： H01L21/0209 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/32134 ,  H01L29/66242

摘要： Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.

公开(公告)号：US20060186437A1

公开(公告)日：2006-08-24

申请号：US11354049

申请日：2006-02-15

申请人： Shigetaka Aoki

发明人： Shigetaka Aoki

IPC分类号： H01L31/109

CPC分类号： H01L29/7322 ,  H01L29/41708 ,  H01L29/7375

摘要： A bipolar transistor, wherein a outgoing electrode is made of a polycrystalline Si film, and C atom, or Ge atom together with C atom are added in the polycrystalline Si film.

摘要翻译： 双极晶体管，其中出射电极由多晶Si膜制成，并且C原子或Ge原子与C原子一起加入到多晶Si膜中。

公开(公告)号：US06762106B2

公开(公告)日：2004-07-13

申请号：US10326059

申请日：2002-12-23

申请人： Shigetaka Aoki ,  Tohru Saitoh ,  Katsuya Nozawa

发明人： Shigetaka Aoki ,  Tohru Saitoh ,  Katsuya Nozawa

IPC分类号： H01L21331

CPC分类号： H01L29/7378 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.

摘要翻译： 包含Si缓冲层，SiGe间隔层，渐变SiGe层和Si覆盖层的Si / SiGe层在对应于集电极开口的区域中外延生长，而多晶层沉积在氮化物膜的上表面上 ，以及氧化膜和氮化物膜的侧表面。 在这种情况下，首先形成Si缓冲层，然后形成诸如SiGe间隔层的其它层，从而确保非选择性外延生长。 然后，在氮化物膜上沉积多晶层。

公开(公告)号：US06717188B2

公开(公告)日：2004-04-06

申请号：US10067866

申请日：2002-02-08

申请人： Shigetaka Aoki

发明人： Shigetaka Aoki

IPC分类号： H01L31072

CPC分类号： H01L29/7378

摘要： A SiGe-HBT is provided with a SiGe film and a Si film grown in succession by epitaxial growth. The SiGe film is made up of a SiGe buffer layer, a SiGe graded composition layer, and a SiGe upper layer, in which the Ge content is substantially constant or changes not more than that of the SiGe graded composition layer. Even if there are fluctuations in the position of the EB junction, the EB junction is positioned in a portion of the SiGe upper layer, so fluctuations in the Ge content in the EB junction can be inhibited, and a stable high current amplification factor can be obtained. It is also possible to provide a SiGeC film instead of the SiGe film.

摘要翻译： SiGe-HBT具有通过外延生长连续生长的SiGe膜和Si膜。 SiGe膜由SiGe缓冲层，SiGe分级组合物层和SiGe上层构成，其中Ge含量基本上恒定或不超过SiGe分级组合物层的变化。 即使EB结的位置发生波动，也可以将EB结位于SiGe上层的一部分，因此能够抑制EB结中的Ge含量的波动，能够稳定的高电流放大系数 获得。 也可以提供SiGeC膜代替SiGe膜。

公开(公告)号：US07579635B2

公开(公告)日：2009-08-25

申请号：US11970089

申请日：2008-01-07

申请人： Shigetaka Aoki

发明人： Shigetaka Aoki

IPC分类号： H01L29/737

CPC分类号： H01L29/7371 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7378

摘要： A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.

摘要翻译： 由SiGe混晶构成的基层包括与集电体层接触形成的间隔层，其中没有扩散基底杂质，并且本征基极层与其中扩散有碱性杂质的发射极层形成接触。 间隔层含有低浓度的C。 本征基层具有在集电极侧含有低浓度C的第一区域和在发射极侧含有高浓度C的第二区域。