公开(公告)号：US20080162978A1

公开(公告)日：2008-07-03

申请号：US11846720

申请日：2007-08-29

申请人： WEN-CHI HSU ,  SHU-HUA KUO ,  HAN-TSUNG LIN ,  MAO-SHIH LI

发明人： WEN-CHI HSU ,  SHU-HUA KUO ,  HAN-TSUNG LIN ,  MAO-SHIH LI

IPC分类号： G06F9/46 ,  G06F1/04

CPC分类号： G06F11/30

摘要： A microcontroller of the present invention integrates a plurality of independent counters of corresponding operation functions into a pool counting circuit and executes each corresponding operation function based on each of different operation cycles. Therefore, the present invention can increase the circuit pool level and reduce the power consumption and the chip size.

摘要翻译： 本发明的微控制器将多个相应操作功能的独立计数器集成到池计数电路中，并且基于每个不同的操作周期执行每个对应的操作功能。 因此，本发明可以增加电路池的电平并降低功耗和芯片尺寸。

公开(公告)号：US07323879B2

公开(公告)日：2008-01-29

申请号：US10711667

申请日：2004-09-30

申请人： Shu-Hua Kuo ,  Jui-Ting Li

发明人： Shu-Hua Kuo ,  Jui-Ting Li

IPC分类号： G01R31/08 ,  G01R31/02

CPC分类号： G01R27/2605 ,  G01R31/318533

摘要： A circuit and method for measuring capacitance and capacitance mismatch of at least one capacitor pair are provided. The circuit includes a first switch, a second switch, a third switch and a P-type transistor. A terminal of the first switch is connected to a terminal of a first capacitor, and a terminal of the second switch is connected to a terminal of a second capacitor. A terminal of the third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor, and a gate of the P-type transistor is connected to another terminal of the third switch. When the first, second and third switches are turned on, a capacitance of the first capacitor, a capacitance of the second capacitor, or a capacitance mismatch between the first and second capacitances is measured.

摘要翻译： 提供了用于测量至少一个电容器对的电容和电容失配的电路和方法。 电路包括第一开关，第二开关，第三开关和P型晶体管。 第一开关的端子连接到第一电容器的端子，第二开关的端子连接到第二电容器的端子。 第三开关的端子连接到第一电容器的另一端子和第二电容器的另一端子，并且P型晶体管的栅极连接到第三开关的另一端子。 当第一，第二和第三开关导通时，测量第一电容器的电容，第二电容器的电容或第一和第二电容之间的电容失配。

公开(公告)号：US20070027647A1

公开(公告)日：2007-02-01

申请号：US11161254

申请日：2005-07-28

申请人： Shu-Hua Kuo ,  Jui-Ting Li ,  Yanan Mou ,  Jiunn-Fu Liu

发明人： Shu-Hua Kuo ,  Jui-Ting Li ,  Yanan Mou ,  Jiunn-Fu Liu

IPC分类号： G01R25/00 ,  G01R29/02

CPC分类号： G01R31/2882

摘要： A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.

摘要翻译： 提供了一种用于测量延迟时间的方法和装置。 首先，产生多个第一/第二相位信号，第一/第二标准信号和第二标准信号的反相信号。 第二标准信号的反相信号被施加到靠近至少相邻的导线的第二导线。 第一/第二标准信号被施加到第一/第二导线以获得第一/第二传输信号。 然后，通过第一/第二相位信号顺序采样第一/第二发送信号，以顺序地获得多个第一/第二采样结果。 通过第一/第二识别级别依次识别第一/第二采样结果，以获得第一/第二识别结果。 因此，可以通过比较不同的第二和第一识别结果来获得第一和第二传输信号之间的延迟时间。

公开(公告)号：US20060085714A1

公开(公告)日：2006-04-20

申请号：US10711667

申请日：2004-09-30

申请人： Shu-Hua Kuo ,  Jui-Ting Li

发明人： Shu-Hua Kuo ,  Jui-Ting Li

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R27/2605 ,  G01R31/318533

摘要： A circuit and method for measuring capacitance and capacitance mismatch of at least one capacitor pair are provided. The circuit comprises a first switch, a second switch, a third switch and a P-type transistor. A terminal of the first switch is connected to a terminal of a first capacitor, and a terminal of the second switch is connected to a terminal of a second capacitor. A terminal of the third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor, and a gate of the P-type transistor is connected to another terminal of the third switch. When the first, second and third switches are turned on, a capacitance of the first capacitor, a capacitance of the second capacitor, or a capacitance mismatch between the first and second capacitances is measured.

摘要翻译： 提供了用于测量至少一个电容器对的电容和电容失配的电路和方法。 该电路包括第一开关，第二开关，第三开关和P型晶体管。 第一开关的端子连接到第一电容器的端子，第二开关的端子连接到第二电容器的端子。 第三开关的端子连接到第一电容器的另一端子和第二电容器的另一端子，并且P型晶体管的栅极连接到第三开关的另一端子。 当第一，第二和第三开关导通时，测量第一电容器的电容，第二电容器的电容或第一和第二电容之间的电容失配。

公开(公告)号：US20060061934A1

公开(公告)日：2006-03-23

申请号：US10711471

申请日：2004-09-21

申请人： Yanan Mou ,  Shu-Hua Kuo ,  Jiunn-Fu Liu

发明人： Yanan Mou ,  Shu-Hua Kuo ,  Jiunn-Fu Liu

IPC分类号： H01G4/008

CPC分类号： H01G4/252 ,  H01G4/012

摘要： A capacitor structure including a conductive layer and a dielectric layer is provided. The conductive layer includes a first pattern and a second pattern arranged alternatively with respect to each other. In addition, the dielectric layer is disposed between the first spiral pattern and the second spiral pattern. Since in the capacitor structure described in the present invention, the first pattern and the second pattern being used as electrodes are disposed in a spiral shape, the capacitance per unit area of the capacitor structure is increased.

摘要翻译： 提供了包括导电层和电介质层的电容器结构。 导电层包括相对于彼此交替布置的第一图案和第二图案。 此外，电介质层设置在第一螺旋图案和第二螺旋图案之间。 由于在本发明中描述的电容器结构中，用作电极的第一图案和第二图案被设置成螺旋形状，因此电容器结构的每单位面积的电容增加。

公开(公告)号：US20080180133A1

公开(公告)日：2008-07-31

申请号：US11698831

申请日：2007-01-29

申请人： Wen-Chi Hsu ,  Shu-Hua Kuo ,  Jia-Jou Tsai ,  Yu-Kuang Wu ,  Zhi-Wei Yang

发明人： Wen-Chi Hsu ,  Shu-Hua Kuo ,  Jia-Jou Tsai ,  Yu-Kuang Wu ,  Zhi-Wei Yang

IPC分类号： H03K19/00 ,  G11C8/10

CPC分类号： G11C8/10

摘要： An expandable decoding circuit includes a latch unit, a latch result selecting unit, and at least one decoding circuit. The latch unit latches raw data and outputs the latch values and the latch inverse-values of the raw data. The latch result selecting unit composes the latch values and the latch inverse-values according to the target decoding value of the decoding unit to generate a pre-decoding value. The latch result selecting unit outputs the pre-decoding value to the corresponding decoding unit. The decoding circuit determines whether a decoding signal is outputted or not according to the pre-decoding value. Thereby, when a new function needs to be added to the deciding circuit, the present invention does not change the original decoding circuit and implements the decoding unit for the new function.

摘要翻译： 可扩展解码电路包括锁存单元，锁存结果选择单元和至少一个解码电路。 锁存单元锁存原始数据并输出原始数据的锁存值和锁存反向值。 锁存结果选择单元根据解码单元的目标解码值构成锁存值和锁存逆值，以生成预解码值。 锁存结果选择单元将预解码值输出到相应的解码单元。 解码电路根据预解码值确定是否输出解码信号。 因此，当需要将新功能添加到判定电路时，本发明不改变原始解码电路并实现新功能的解码单元。

公开(公告)号：US07057873B2

公开(公告)日：2006-06-06

申请号：US10711471

申请日：2004-09-21

申请人： Yanan Mou ,  Shu-Hua Kuo ,  Jiunn-Fu Liu

发明人： Yanan Mou ,  Shu-Hua Kuo ,  Jiunn-Fu Liu

IPC分类号： H01G4/32

CPC分类号： H01G4/252 ,  H01G4/012

摘要： A capacitor structure including a conductive layer and a dielectric layer is provided. The conductive layer includes a first pattern and a second pattern arranged alternatively with respect to each other. In addition, the dielectric layer is disposed between the first spiral pattern and the second spiral pattern. Since in the capacitor structure described in the present invention, the first pattern and the second pattern being used as electrodes are disposed in a spiral shape, the capacitance per unit area of the capacitor structure is increased.

摘要翻译： 提供了包括导电层和电介质层的电容器结构。 导电层包括相对于彼此交替布置的第一图案和第二图案。 此外，电介质层设置在第一螺旋图案和第二螺旋图案之间。 由于在本发明中描述的电容器结构中，用作电极的第一图案和第二图案被设置成螺旋形状，因此电容器结构的每单位面积的电容增加。

公开(公告)号：US06265892B1

公开(公告)日：2001-07-24

申请号：US09371199

申请日：1999-08-10

申请人： Shyh-Jye Jou ,  Ray-De Chiao ,  Shu-Hua Kuo ,  Tin-Hao Lin

发明人： Shyh-Jye Jou ,  Ray-De Chiao ,  Shu-Hua Kuo ,  Tin-Hao Lin

IPC分类号： H03K1716

CPC分类号： H03K17/167

摘要： A low noise output buffer to simultaneously reduce switching noise and output signal ringing for output ringing and maintain DC current. A temporary and a steady-state output buffers are supplied by a buffer voltage source and an internal circuit voltage source, respectively. Each driver has a pull-up and a pull-down transistors. While switching the output buffer from a high voltage level to a low voltage level or from a low voltage level to a high voltage level, a predriver and a single steady-state circuit are designed to respectively generate a large simultaneous switching noise at the buffer voltage source and a small simultaneous switching noise at the internal circuit voltage source. A Schmitt trigger circuit is also used to turn off the temporary driver, so as to reduce the output signal ringing while the steady-state driver maintains a supply of DC current. In another design of a low noise output buffer to reduce ground bounces and output signal ringing as well as to maintain a DC current, a temporary driver is used. An adaptive characteristic of the low noise output buffer under different loading conditions is achieved by a feedback circuit. The temporary driver is turned on only during the middle period of output transition time to provide an additional charging or discharging current. Since the temporary driver is always off apart from the transition period, the effect of reducing ground bounces and output signal ringing can thus be outstanding.

摘要翻译： 低噪声输出缓冲器，可同时降低开关噪声和输出信号振铃以进行输出振铃并保持直流电流。 分别由缓冲电压源和内部电路电压源提供临时和稳态输出缓冲器。 每个驱动器都有一个上拉和一个下拉晶体管。 当将输出缓冲器从高电压电平切换到低电压电平或从低电压电平切换到高电压电平时，预驱动器和单稳态电路被设计为分别在缓冲电压下产生大的同时开关噪声 源极和内部电路电压源的小的同时开关噪声。 施密特触发电路也用于关断临时驱动器，以便在稳态驱动器保持直流电流供应时减少输出信号振铃。 在另一种低噪声输出缓冲器的设计中，为了减少地面跳动和输出信号振铃以及维持直流电流，使用临时驱动器。 通过反馈电路实现了不同负载条件下低噪声输出缓冲器的自适应特性。 临时驱动器仅在输出转换时间的中间期间接通，以提供额外的充电或放电电流。 由于临时驾驶员始终偏离过渡期，所以减少地面反弹和输出信号振铃的效果因此可以突出。

公开(公告)号：US20080155291A1

公开(公告)日：2008-06-26

申请号：US11963735

申请日：2007-12-21

申请人： Wen-Chi Hsu ,  Shu-Hua Kuo ,  Chao-Chung Chang ,  Rong-Yau Tsai ,  Jia-Jou Tsai

发明人： Wen-Chi Hsu ,  Shu-Hua Kuo ,  Chao-Chung Chang ,  Rong-Yau Tsai ,  Jia-Jou Tsai

IPC分类号： G06F1/32

CPC分类号： G06F1/24

摘要： A method for resetting a micro controller is disclosed. The method uses an improved micro controller reset circuit designed for loading micro controller options regardless of whether a reset key is pressed after the power is turned on. In this method, the initial values of the micro controller are recovered so as to reduce power consumption and avoid conflict between signals.

摘要翻译： 公开了一种用于复位微控制器的方法。 该方法使用设计用于加载微控制器选项的改进的微控制器复位电路，而不管在接通电源后是否按下复位键。 在该方法中，恢复微控制器的初始值，以便降低功耗并避免信号之间的冲突。

公开(公告)号：US07246019B2

公开(公告)日：2007-07-17

申请号：US11161254

申请日：2005-07-28

申请人： Shu-Hua Kuo ,  Jui-Ting Li ,  Yanan Mou ,  Jiunn-Fu Liu

发明人： Shu-Hua Kuo ,  Jui-Ting Li ,  Yanan Mou ,  Jiunn-Fu Liu

IPC分类号： G01R21/00

CPC分类号： G01R31/2882

摘要： A method and apparatus for measuring a delay time is provided. First, a plurality of first/second phase signals, a first/second standard signal, and an inverse signal of the second standard signal are generated. The inverse signal of the second standard signal is applied to a second conductive line close to at least an adjacent conductive line. The first/second standard signal is applied to the first/second conductive line to obtain a first/second transmission signal. Then, the first/second transmission signal is sequentially sampled by the first/second phase signals to sequentially obtain a plurality of first/second sampling results. The first/second sampling results are sequentially identified by a first/second identifying level to obtain a first/second identification result. Accordingly, the delay time between the first and the second transmission signal may be obtained by comparing the different the second and the first identification result.

摘要翻译： 提供了一种用于测量延迟时间的方法和装置。 首先，产生多个第一/第二相位信号，第一/第二标准信号和第二标准信号的反相信号。 第二标准信号的反相信号被施加到靠近至少相邻的导线的第二导线。 第一/第二标准信号被施加到第一/第二导线以获得第一/第二传输信号。 然后，通过第一/第二相位信号顺序采样第一/第二发送信号，以顺序地获得多个第一/第二采样结果。 通过第一/第二识别级别依次识别第一/第二采样结果，以获得第一/第二识别结果。 因此，可以通过比较不同的第二和第一识别结果来获得第一和第二传输信号之间的延迟时间。