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    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory
    2.
    发明授权
    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
    数据传输电路，数据线驱动电路，放大电路，半导体集成电路和半导体存储器

    公开(公告)号：US5680366A

    公开(公告)日：1997-10-21

    申请号：US573133

    申请日：1995-12-15

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03K3/26

    CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

    摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

    Semiconductor integrated circuit with a data transmission circuit
    5.
    发明授权
    Semiconductor integrated circuit with a data transmission circuit 失效
    具有数据传输电路的半导体集成电路

    公开(公告)号：US5642323A

    公开(公告)日：1997-06-24

    申请号：US573076

    申请日：1995-12-15

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

    摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

    Semiconductor memory device having a prolonged data holding time
    6.
    发明授权
    Semiconductor memory device having a prolonged data holding time 失效
    半导体存储器件具有延长的数据保持时间

    公开(公告)号：US5426601A

    公开(公告)日：1995-06-20

    申请号：US184933

    申请日：1994-01-24

    申请人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    发明人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C5/143

    摘要： An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell. This adequately prolongs the data-holding time with no sacrifice in memory cell voltage resistance.

    摘要翻译： 外部电源电压VCC作为第一内部电源电压VPERI施加到外围电路。 如果VCC在VCC推荐工作条件下规定的电压范围内VCC不大于下限电压V0L，则电源电压控制电路输出高逻辑电平的电压控制信号VSIG，否则输出低逻辑电平的VSIG。 电源电路将第二内部电源电压VW和第三内部电源电压VWORD施加到存储单元部分。 如果VSIG为高电平，则VW等于VPERI，而另一方面，VW是VPERI升压的电压。 VWORD是由于将VW进一步升高而产生的电压。 行解码器将VW发送到一行读出放大器的使能信号线上，并将VWORD发送到存储单元阵列的字线上，以使VW成为存储单元的高逻辑电平数据写入电压。 这样就可以在不牺牲存储单元耐压的情况下充分延长数据保持时间。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5546346A

    公开(公告)日：1996-08-13

    申请号：US354124

    申请日：1994-12-06

    申请人： Masashi Agata ,  Kazuhiro Matsuyama ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    发明人： Masashi Agata ,  Kazuhiro Matsuyama ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C7/1072

    摘要： In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.

    摘要翻译： 在需要与时钟信号同步执行高速连续操作的同步DRAM中，DBI线对连接在DQ线对和RDB线对之间，其流水线操作的单周期时间为 分为四个阶段。 该S-DRAM具有以下：第一预充电电路，用于仅在第一和第四周期中将DQ线对预充电或电压均衡至电源电压电平; 第二预充电电路，用于仅在第一和第二周期中将DBI线对对电压均衡至接地电压电平; 第三预充电电路，用于仅在第一和第二周期中将RDB线对对电压均衡至电源电压电平; 第一和第二差分放大器，用于在第三周期中将DQ线上的数据发送到DBI线上，并且用于在第四周期中将数据保存在DBI线上; 以及第三差分放大器，其在第三周期中将DBI线上的数据发送到RDB线上，并且在第四周期中将数据保存在RDB线上。

    Semiconductor memory
    9.
    发明授权
    Semiconductor memory 失效

    公开(公告)号：US5835424A

    公开(公告)日：1998-11-10

    申请号：US833754

    申请日：1997-04-09

    申请人： Hirohito Kikukawa ,  Masashi Agata ,  Hironori Akamatsu

    发明人： Hirohito Kikukawa ,  Masashi Agata ,  Hironori Akamatsu

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C29/84

    摘要： In a synchronous DRAM, a redundancy judging circuit has a frequency dividing circuit and a plurality of judging circuits each having two address comparing circuits and one output circuit. When an internal CAS signal having an activating period of time according to a data burst length, is activated, the frequency dividing circuit divides the frequency of an internal continuous clock signal having the same time period of one cycle and the same phase as those of an external clock signal, and generates complementary clock signals each having a time period of one cycle twice the time period of one cycle of the internal continuous clock signal. A pair of address comparing circuits to which supplied is an internal column address to be successively updated according to the data burst length, alternately supply a redundancy judgement signal after alternately comparing the same defective column address previously programmed therein, with an internal column address according to the complementary clock signals supplied from the frequency dividing circuit. The output circuit supplies a redundancy judgement signal when either of the judgement signals is obtained. Thus, there is made an accurate column redundancy judgement at the time when the external clock signal is high in frequency.

    Semiconductor memory
    10.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5717651A

    公开(公告)日：1998-02-10

    申请号：US521651

    申请日：1995-08-31

    申请人： Hirohito Kikukawa ,  Masashi Agata ,  Hironori Akamatsu

    发明人： Hirohito Kikukawa ,  Masashi Agata ,  Hironori Akamatsu

    IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

    CPC分类号： G11C29/84

    摘要： In a synchronous DRAM, a redundancy judging circuit has a frequency dividing circuit and a plurality of judging circuits each having two address comparing circuits and one output circuit. When an internal CAS signal having an activating period of time according to a data burst length, is activated, the frequency dividing circuit divides the frequency of an internal continuous clock signal having the same time period of one cycle and the same phase as those of an external clock signal, and generates complementary clock signals each having a time period of one cycle twice the time period of one cycle of the internal continuous clock signal. A pair of address comparing circuits to which supplied is an internal column address to be successively updated according to the data burst length, alternately supply a redundancy judgement signal after alternately comparing the same defective column address previously programmed therein, with an internal column address according to the complementary clock signals supplied from the frequency dividing circuit. The output circuit supplies a redundancy judgement signal when either of the judgement signals is obtained. Thus, there is made an accurate column redundancy judgement at the time when the external clock signal is high in frequency.

    摘要翻译： 在同步DRAM中，冗余判断电路具有分频电路和多个判断电路，每个判断电路具有两个地址比较电路和一个输出电路。 当激活具有根据数据突发长度的激活时间段的内部CAS信号时，分频电路将具有与一个周期相同的时间周期和相同相位的内部连续时钟信号的频率划分为 外部时钟信号，并产生互补时钟信号，每个互补时钟信号具有一个周期的时间周期是内部连续时钟信号的一个周期的时间周期的两倍。 提供的一对地址比较电路是根据数据突发长度连续更新的内部列地址，交替地将先前编程的相同的缺陷列地址与根据 从分频电路提供的互补时钟信号。 当获得任一判断信号时，输出电路提供冗余判断信号。 因此，在外部时钟信号的频率高的时候，进行精确的列冗余判定。