公开(公告)号：US5719531A

公开(公告)日：1998-02-17

申请号：US739841

申请日：1996-10-30

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03F3/45

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

公开(公告)号：US5642323A

公开(公告)日：1997-06-24

申请号：US573076

申请日：1995-12-15

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

公开(公告)号：US5818782A

公开(公告)日：1998-10-06

申请号：US814507

申请日：1997-03-10

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C13/00

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

公开(公告)号：US5680366A

公开(公告)日：1997-10-21

申请号：US573133

申请日：1995-12-15

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03K3/26

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

公开(公告)号：US5515334A

公开(公告)日：1996-05-07

申请号：US260922

申请日：1994-06-15

申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

公开(公告)号：US5983331A

公开(公告)日：1999-11-09

申请号：US943411

申请日：1997-09-30

申请人： Hironori Akamatsu ,  Toshio Yamada ,  Hisakazu Kotani ,  Yoshiro Nakata

发明人： Hironori Akamatsu ,  Toshio Yamada ,  Hisakazu Kotani ,  Yoshiro Nakata

IPC分类号： G06F15/78 ,  G11C11/401 ,  G06F12/00

CPC分类号： G06F15/7832

摘要： A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.

摘要翻译： 作为母芯片的CPU与作为辅助芯片的DRAM组合安装。 模式输出电路能够设置DRAM的存储容量以及用于通过DRAM的模式输出端和CPU的模式输入端转发到CPU的模式输入电路的DRAM的刷新周期。 CPU根据来自模式输入电路的数据控制地址生成器，根据DRAM存储容量和DRAM刷新周期设定用于存取DRAM的地址数据的位数。

公开(公告)号：US5545977A

公开(公告)日：1996-08-13

申请号：US74561

申请日：1993-06-09

申请人： Toshio Yamada ,  Akinori Shibayama ,  Shunichi Iwanari ,  Atsushi Fujiwara

发明人： Toshio Yamada ,  Akinori Shibayama ,  Shunichi Iwanari ,  Atsushi Fujiwara

IPC分类号： G05F1/24 ,  G05F1/613 ,  G05F3/24 ,  G11C11/407 ,  G11C11/408 ,  H01L27/10 ,  H03K19/00 ,  G05F3/22

CPC分类号： G05F3/245 ,  Y10S323/907

摘要： In a circuit, a resistance element is interposed between a positive power supply line (external power supply voltage level VCC) and an output node. To feedback an output potential, there is disposed an N-type MOSFET of which gate is connected to the output node and of which source is connected to the earth line (earth potential VSS) in the circuit. Another three N-type MOSFETs which are so connected in series to one another as to form a MOS diode, are interposed between the drain of the feedback N-type MOSFET and the output node. The earth line also serves as a reference potential line for the potential of the output node. Variations of the threshold voltages of the MOSFETs due to temperature variations are compensated. This restrains the output potential from varying.

摘要翻译： 在电路中，在正电源线（外部电源电压电平VCC）和输出节点之间插入电阻元件。 为了反馈输出电位，设置了一个N型MOSFET，其栅极连接到输出节点，并且其中的源极连接到电路中的地线（地电位VSS）。 在反馈N型MOSFET的漏极和输出节点之间插入另外三个彼此串联连接形成MOS二极管的N型MOSFET。 地线也可作为输出节点电位的参考电位线。 由于温度变化导致的MOSFET的阈值电压的变化被补偿。 这就抑制了输出电位的变化。

公开(公告)号：US06285723B1

公开(公告)日：2001-09-04

申请号：US09513714

申请日：2000-02-25

申请人： Toshio Yamada ,  Masashi Agata

发明人： Toshio Yamada ,  Masashi Agata

IPC分类号： H04L700

CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286

摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.

摘要翻译： 根据本发明的定时信号产生电路包括：延迟电路，用于在延迟时钟信号的同时传输输入时钟信号，延迟电路具有多个中间抽头，能够在延迟电路的相应位置输出时钟信号 ; 用于在延迟时钟信号的同时发送时钟信号的检测延迟电路，所述检测延迟电路具有能够在其检测延迟电路中的相应位置处输出时钟信号的多个中间抽头; 多个采样/保持电路，每个采样/保持电路均具有采样信号端子，采样信号端子连接到检测延迟电路的多个中间抽头中的相应的一个; 用于检测时钟信号的边沿的多个边界延迟电路，边界检测电路连接到取样/保持电路的各个输出端; 以及输出选择电路，用于经由根据由边界检测电路检测的时钟信号的边缘位置选择的多个中间抽头中的至少一个提取时钟信号，输出选择电路将提取的时钟信号作为定时输出 信号。

公开(公告)号：US5892384A

公开(公告)日：1999-04-06

申请号：US658931

申请日：1996-05-31

申请人： Toshio Yamada ,  Masashi Agata

发明人： Toshio Yamada ,  Masashi Agata

IPC分类号： G11C7/00 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K3/02 ,  H03K3/10 ,  H03K5/13 ,  H03K5/131 ,  H03K5/19 ,  H04L7/00 ,  H03H11/26

CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286

摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.

公开(公告)号：US06181620B2

公开(公告)日：2001-01-30

申请号：US09484023

申请日：2000-01-18

申请人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

发明人： Masashi Agata ,  Kazunari Takahashi ,  Tsutomu Fujita ,  Naoki Kuroda ,  Toshio Yamada

IPC分类号： G11C1124

CPC分类号： G11C11/405 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

摘要： The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

摘要翻译： 本发明的半导体存储装置包括具有两个晶体管和一个存储电容器的存储单元。 每个存储单元与第一字线和用于第一端口的第一位线和用于第二端口的第二字线和第二位线连接。 第一位线和第二位线以开放位线配置交替布置。 在半导体存储装置的动作中，在对第一读出放大器的第一预定电荷进行预充电的第一预充电信号或激活第一读出放大器的第一读出放大器的激活信号保持为有效状态的期间内， 第二位线和用于激活第二读出放大器的第二读出放大器激活信号都处于非活动状态。