公开(公告)号：US20150035025A1

公开(公告)日：2015-02-05

申请号：US14516201

申请日：2014-10-16

申请人： Bong-Soo KIM ,  Soo-Ho SHIN ,  Ho-In RYU ,  Hyeong-Sun HONG

发明人： Bong-Soo KIM ,  Soo-Ho SHIN ,  Ho-In RYU ,  Hyeong-Sun HONG

IPC分类号： H01L29/78 ,  H01L27/108

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US08648423B2

公开(公告)日：2014-02-11

申请号：US13239461

申请日：2011-09-22

申请人： Sung-Hee Han ,  Soo-Ho Shin

发明人： Sung-Hee Han ,  Soo-Ho Shin

IPC分类号： H01L23/48 ,  H01L27/088 ,  H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/10885 ,  H01L27/10894

摘要： Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns. The second bit line structures include second bit line conductive patterns configured to contact the bit line contact plugs to be substantially parallel to the first bit line conductive patterns and first bit line spacers covering sidewalls of the second bit line conductive patterns and sidewalls of the bit line contact plugs.

摘要翻译： 提供了一种半导体器件，其中可以增加存储接触插塞和位线接触插头之间的短边。 该器件包括：衬底，其包括由隔离区域限定的隔离区域和有源区域，栅极设置在衬底中并且被配置为与有源区域相交并且限定有源区域中的源极区域和漏极区域，设置在衬底上的层间绝缘层， 配置为穿透层间绝缘层并接触漏极区的位线接触插塞以及设置在层间绝缘层上的第一位线结构和第二位线结构。 第一位线结构包括第一位线导电图案和覆盖第一位线导电图案的侧壁的第一位线间隔件。 第二位线结构包括第二位线导电图案，其被配置为接触位线接触插塞以基本上平行于第一位线导电图案，第一位线间隔件覆盖位线的第二位线导电图案和侧壁的侧壁 接触插头

公开(公告)号：US20130248984A1

公开(公告)日：2013-09-26

申请号：US13899911

申请日：2013-05-22

申请人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin

发明人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

摘要： A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

公开(公告)号：US08183113B2

公开(公告)日：2012-05-22

申请号：US12784977

申请日：2010-05-21

申请人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin ,  Eun-Cheol Lee

发明人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin ,  Eun-Cheol Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/4236 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66621

摘要： A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.

摘要翻译： 半导体器件中的凹陷栅极结构包括部分地埋在衬底中的栅电极，形成在栅极的掩埋部分中的阻挡构件以及形成在栅电极和衬底之间的栅极绝缘层。 阻挡构件可以有效地防止栅极电极的掩埋部分中的空隙或接缝在随后的制造工艺中接触与沟道区域相邻的栅极绝缘层。 因此，半导体器件可以具有规则的阈值电压，并且通过空隙或接缝的漏电流可以有效地降低。

公开(公告)号：US20120091532A1

公开(公告)日：2012-04-19

申请号：US13239461

申请日：2011-09-22

申请人： Sung-Hee Han ,  Soo-Ho Shin

发明人： Sung-Hee Han ,  Soo-Ho Shin

IPC分类号： H01L27/088 ,  H01L23/48

CPC分类号： H01L27/10888 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/10885 ,  H01L27/10894

摘要： Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns. The second bit line structures include second bit line conductive patterns configured to contact the bit line contact plugs to be substantially parallel to the first bit line conductive patterns and first bit line spacers covering sidewalls of the second bit line conductive patterns and sidewalls of the bit line contact plugs.

摘要翻译： 提供了一种半导体器件，其中可以增加存储接触插塞和位线接触插头之间的短边。 该器件包括：衬底，其包括由隔离区域限定的隔离区域和有源区域，栅极设置在衬底中并且被配置为与有源区域相交并且限定有源区域中的源极区域和漏极区域，设置在衬底上的层间绝缘层， 配置为穿透层间绝缘层并接触漏极区的位线接触插塞以及设置在层间绝缘层上的第一位线结构和第二位线结构。 第一位线结构包括第一位线导电图案和覆盖第一位线导电图案的侧壁的第一位线间隔件。 第二位线结构包括第二位线导电图案，其被配置为接触位线接触插塞以基本上平行于第一位线导电图案，第一位线间隔件覆盖位线的第二位线导电图案和侧壁的侧壁 接触插头

公开(公告)号：US07767531B2

公开(公告)日：2010-08-03

申请号：US12418359

申请日：2009-04-03

申请人： Soo-Ho Shin ,  Jin-Woo Lee ,  Eun-Cheol Lee

发明人： Soo-Ho Shin ,  Jin-Woo Lee ,  Eun-Cheol Lee

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/3205

CPC分类号： H01L27/10873 ,  H01L27/10891 ,  H01L29/66787

摘要： According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern.

摘要翻译： 根据本发明的一些实施例，形成晶体管的方法包括在半导体衬底中形成器件隔离层。 形成器件隔离层以限定至少一个有源区。 沟道区形成在半导体衬底的有源区的预定部分中。 形成两个通道部分孔，从半导体衬底的主表面向下延伸以与沟道区相接触。 栅极图案填充沟道部分孔并穿过有源区。 所得到的晶体管能够确保恒定的阈值电压，而不受沟道部分孔和栅极图案的取向状态的影响。

公开(公告)号：US07629215B2

公开(公告)日：2009-12-08

申请号：US12128682

申请日：2008-05-29

申请人： Soo-Ho Shin ,  Sun-Hoo Park ,  Byung-Hyug Roh ,  Young-Woong Son ,  Sang-Wook Lee

发明人： Soo-Ho Shin ,  Sun-Hoo Park ,  Byung-Hyug Roh ,  Young-Woong Son ,  Sang-Wook Lee

IPC分类号： H01L21/8238 ,  H01L31/062

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

摘要翻译： 半导体器件包括第一栅极结构，第二栅极结构，第一覆盖层图案，第二覆盖层图案，第一间隔物，第二间隔物，第三间隔物以及具有第一杂质区和第二杂质区的衬底。 第一栅极结构以第一间距布置在衬底上。 第二栅极结构以大于第一间距的第二间距布置在衬底上。 第一覆盖层图案具有沿着第一栅极结构的侧面延伸的段和沿着衬底延伸的段。 第二覆盖层图案具有沿着第二栅极结构延伸的段和沿着衬底延伸的段。 第一间隔物和第二间隔物层叠在第二覆盖层图案上。 第三间隔物形成在第一覆盖层图案上。

公开(公告)号：US07300888B2

公开(公告)日：2007-11-27

申请号：US10008700

申请日：2001-12-07

申请人： Hong-sik Jeong ,  Soo-ho Shin ,  Won-suk Yang ,  Ki-nam Kim

发明人： Hong-sik Jeong ,  Soo-ho Shin ,  Won-suk Yang ,  Ki-nam Kim

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/316 ,  H01L21/76895 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.

摘要翻译： 通过在基板上形成绝缘层来制造集成电路器件。 在绝缘层上形成覆盖层，并对覆盖层和绝缘层进行图案化。 绝缘垫片形成在绝缘层的侧壁上，使得绝缘隔离物，覆盖层和衬底包围绝缘层。

公开(公告)号：US20060289931A1

公开(公告)日：2006-12-28

申请号：US11507753

申请日：2006-08-22

申请人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin ,  Eun-Cheol Lee

发明人： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin ,  Eun-Cheol Lee

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/945 ,  H01L21/7624 ,  H01L29/4236 ,  H01L29/66181 ,  H01L29/66621 ,  H01L29/7834

摘要： A recessed gate structure in a semiconductor device includes a gate electrode partially buried in a substrate, a blocking member formed in the buried portion of the gate electrode, and a gate insulation layer formed between the gate electrode and the substrate. The blocking member may effectively prevent a void or a seam in the buried portion of the gate electrode from contacting the gate insulation layer adjacent to a channel region in subsequent manufacturing processes. Thus, the semiconductor device may have a regular threshold voltage and a leakage current passing through the void or the seam may efficiently decrease.

摘要翻译： 半导体器件中的凹陷栅极结构包括部分地埋在衬底中的栅电极，形成在栅极的掩埋部分中的阻挡构件以及形成在栅电极和衬底之间的栅极绝缘层。 阻挡构件可以有效地防止栅极电极的掩埋部分中的空隙或接缝在随后的制造工艺中接触与沟道区域相邻的栅极绝缘层。 因此，半导体器件可以具有规则的阈值电压，并且通过空隙或接缝的漏电流可以有效地降低。

公开(公告)号：US20050282343A1

公开(公告)日：2005-12-22

申请号：US11156271

申请日：2005-06-17

申请人： Soo-Ho Shin ,  Jin-Woo Lee ,  Eun-Cheol Lee

发明人： Soo-Ho Shin ,  Jin-Woo Lee ,  Eun-Cheol Lee

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L27/10873 ,  H01L27/10891 ,  H01L29/66787

摘要： According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern.

摘要翻译： 根据本发明的一些实施例，形成晶体管的方法包括在半导体衬底中形成器件隔离层。 形成器件隔离层以限定至少一个有源区。 沟道区形成在半导体衬底的有源区的预定部分中。 形成两个通道部分孔，从半导体衬底的主表面向下延伸以与沟道区相接触。 栅极图案填充沟道部分孔并穿过有源区。 所得到的晶体管能够确保恒定的阈值电压，而不受沟道部分孔和栅极图案的取向状态的影响。