公开(公告)号：US07629215B2

公开(公告)日：2009-12-08

申请号：US12128682

申请日：2008-05-29

申请人： Soo-Ho Shin ,  Sun-Hoo Park ,  Byung-Hyug Roh ,  Young-Woong Son ,  Sang-Wook Lee

发明人： Soo-Ho Shin ,  Sun-Hoo Park ,  Byung-Hyug Roh ,  Young-Woong Son ,  Sang-Wook Lee

IPC分类号： H01L21/8238 ,  H01L31/062

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

摘要翻译： 半导体器件包括第一栅极结构，第二栅极结构，第一覆盖层图案，第二覆盖层图案，第一间隔物，第二间隔物，第三间隔物以及具有第一杂质区和第二杂质区的衬底。 第一栅极结构以第一间距布置在衬底上。 第二栅极结构以大于第一间距的第二间距布置在衬底上。 第一覆盖层图案具有沿着第一栅极结构的侧面延伸的段和沿着衬底延伸的段。 第二覆盖层图案具有沿着第二栅极结构延伸的段和沿着衬底延伸的段。 第一间隔物和第二间隔物层叠在第二覆盖层图案上。 第三间隔物形成在第一覆盖层图案上。

公开(公告)号：US07701002B2

公开(公告)日：2010-04-20

申请号：US11608482

申请日：2006-12-08

申请人： Hyeong-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Young-Woong Son

发明人： Hyeong-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Young-Woong Son

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/4236 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device includes an isolation layer disposed in a semiconductor device to define an active region. A gate trench is disposed across the active region and extends to the isolation layer. An insulated gate electrode fills a portion of the gate trench and covers at least one sidewall of the active region. A portion of the gate electrode, that covers at least one sidewall of the active region, extends under a portion of the gate electrode that crosses the active region. An insulating pattern is disposed on the gate electrode.

摘要翻译： 半导体器件包括设置在半导体器件中以限定有源区的隔离层。 栅极沟槽横跨有源区域设置并延伸到隔离层。 绝缘栅电极填充栅极沟槽的一部分并覆盖有源区的至少一个侧壁。 覆盖有源区的至少一个侧壁的栅电极的一部分在与有源区交叉的栅电极的一部分之下延伸。 绝缘图案设置在栅电极上。

公开(公告)号：US08895400B2

公开(公告)日：2014-11-25

申请号：US13473751

申请日：2012-05-17

申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

IPC分类号： H01L21/331 ,  H01L27/108 ,  H01L21/74 ,  H01L21/311

CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

公开(公告)号：US20080079070A1

公开(公告)日：2008-04-03

申请号：US11797137

申请日：2007-05-01

申请人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7851 ,  H01L27/10826 ,  H01L27/10891 ,  H01L27/24 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7853

摘要： A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.

摘要翻译： 公开了具有具有成形栅极沟槽的掩埋栅极线的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底中以限定多表面有源区/沟道的沟槽隔离层。 延伸到沟槽隔离层的栅极线填充栅极沟槽的一部分。 栅极沟槽形成有一系列凹陷以容纳通道中的峰值。 凹陷/峰值的组合用于增加通道的有效面积，从而能够在不增加其宽度的情况下形成更小的沟道半导体器件。

公开(公告)号：US20080003753A1

公开(公告)日：2008-01-03

申请号：US11608482

申请日：2006-12-08

申请人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Young-Woong Son

发明人： Hyeoung-Won Seo ,  Jae-Man Yoon ,  Kang-Yoon Lee ,  Young-Woong Son

IPC分类号： H01L21/336

CPC分类号： H01L29/4236 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device includes an isolation layer disposed in a semiconductor device to define an active region. A gate trench is disposed across the active region and extends to the isolation layer. An insulated gate electrode fills a portion of the gate trench and covers at least one sidewall of the active region. A portion of the gate electrode, that covers at least one sidewall of the active region, extends under a portion of the gate electrode that crosses the active region. An insulating pattern is disposed on the gate electrode.

摘要翻译： 半导体器件包括设置在半导体器件中以限定有源区的隔离层。 栅极沟槽横跨有源区域设置并延伸到隔离层。 绝缘栅电极填充栅极沟槽的一部分并覆盖有源区的至少一个侧壁。 覆盖有源区的至少一个侧壁的栅电极的一部分在与有源区交叉的栅电极的一部分之下延伸。 绝缘图案设置在栅电极上。

公开(公告)号：US20120264280A1

公开(公告)日：2012-10-18

申请号：US13473751

申请日：2012-05-17

申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

IPC分类号： H01L21/768

CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。

公开(公告)号：US07619281B2

公开(公告)日：2009-11-17

申请号：US11797137

申请日：2007-05-01

申请人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Young-Woong Son ,  Kang-Yoon Lee ,  Bong-Soo Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7851 ,  H01L27/10826 ,  H01L27/10891 ,  H01L27/24 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7853

摘要： A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.

摘要翻译： 公开了具有具有成形栅极沟槽的掩埋栅极线的半导体器件及其制造方法。 半导体器件包括设置在半导体衬底中以限定多表面有源区/沟道的沟槽隔离层。 延伸到沟槽隔离层的栅极线填充栅极沟槽的一部分。 栅极沟槽形成有一系列凹陷以容纳通道中的峰值。 凹陷/峰值的组合用于增加通道的有效面积，从而能够在不增加其宽度的情况下形成更小的沟道半导体器件。

公开(公告)号：US20080048333A1

公开(公告)日：2008-02-28

申请号：US11842416

申请日：2007-08-21

申请人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

发明人： Hyeoung-Won Seo ,  Yun-Gi Kim ,  Young-Woong Son ,  Bong-Soo Kim

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L27/10891 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

摘要翻译： 半导体器件包括具有限定在其中的单元区域和外围电路区域的半导体衬底。 掩埋字线设置在单元区域中的基板中，并且具有比单元区域中的单元有源区域的顶表面低的顶表面。 栅极线设置在外围电路区域中的衬底上。 字线互连设置在外围电路区域中的衬底中，字线互连包括接触掩埋字线的第一部分，并且具有低于电池有源区的顶表面的顶表面和重叠的第二部分 通过并与栅极线接触。