公开(公告)号：US07573297B1

公开(公告)日：2009-08-11

申请号：US11609257

申请日：2006-12-11

申请人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

发明人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

摘要翻译： 用于新的路由结构和方法的方法和装置，其改善了用户定义的功能对可编程逻辑设备的拟合。 特别是第二次装配得到改善。 示例性结构和方法包括通过提供多个扩展和旁路路径允许使用来自多于一个相邻宏小区的输入扩展产品术语。 此外，产品术语“或”移位可防止宏单元输出级被掩埋并使其不可访问，并且在扩展器字线上提供宏单元输出，提高这些线路的效率以及节省路由资源。 扩展，旁路，或移位和扩展器字线可以以逻辑阵列块边界终止，或者可以超出这些边界到其他逻辑阵列块。

公开(公告)号：US06836144B1

公开(公告)日：2004-12-28

申请号：US10206250

申请日：2002-07-26

申请人： John Henry Bui ,  John Costello ,  Stephanie Tran

发明人： John Henry Bui ,  John Costello ,  Stephanie Tran

IPC分类号： H03K512

CPC分类号： H03K19/00384 ,  H04L25/0278

摘要： Circuits may provide series on-chip termination impedance to one or more input/output pins. In one embodiment, two off-chip reference resistors in combination with internal calibration circuitry are used to control termination transistors coupled to several input/output (I/O) pins. The termination transistors behave as programmably adjustable termination resistors that match the impedance of external resistors. By using only a small number of reference resistors (e.g., 2 resistors) for a large number of I/O pins, the present invention eliminates the external components that would otherwise be needed to provide resistance termination. The effective series termination resistance may be programmed, enabling the termination resistance to meet different I/O standards. Further, the resistance termination techniques of the present invention are not sensitive to process, voltage supply, and temperature (PVT) variations.

摘要翻译： 电路可以向一个或多个输入/输出引脚提供串联片上终止阻抗。 在一个实施例中，两个片外参考电阻器与内部校准电路组合用于控制耦合到多个输入/输出（I / O）引脚的端接晶体管。 端接晶体管表现为与外部电阻的阻抗匹配的可编程可调终端电阻。 通过仅使用少量的用于大量I / O引脚的参考电阻（例如，2个电阻），本发明消除了否则将需要提供电阻终止的外部组件。 可编程有效串联端接电阻，使终端电阻能够满足不同的I / O标准。 此外，本发明的电阻终止技术对于工艺，电压供应和温度（PVT）变化不敏感。

公开(公告)号：US20070279817A1

公开(公告)日：2007-12-06

申请号：US11890933

申请日：2007-08-07

申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

公开(公告)号：US06927601B1

公开(公告)日：2005-08-09

申请号：US10301506

申请日：2002-11-21

申请人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

发明人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

摘要翻译： 用于新的路由结构和方法的方法和装置，其改善了用户定义的功能对可编程逻辑设备的拟合。 特别是第二次装配得到改善。 示例性结构和方法包括通过提供多个扩展和旁路路径允许使用来自多于一个相邻宏小区的输入扩展产品术语。 此外，产品术语“或”移位可以防止宏单元输出级被掩埋并使其无法访问，并且在扩展器字线上提供宏单元输出，提高这些线路的效率，并节省路由资源。 扩展，旁路，或移位和扩展器字线可以以逻辑阵列块边界终止，或者可以超出这些边界到其他逻辑阵列块。

公开(公告)号：US6072358A

公开(公告)日：2000-06-06

申请号：US8619

申请日：1998-01-16

申请人： Chuan-Yung Hung ,  John Costello ,  Stephanie Tran ,  Guu Lin ,  Mark Fiester

发明人： Chuan-Yung Hung ,  John Costello ,  Stephanie Tran ,  Guu Lin ,  Mark Fiester

IPC分类号： G11C5/14 ,  G11C16/12 ,  G06F3/02

CPC分类号： G11C16/12 ,  G11C5/145

摘要： Improved charge pump circuitry that significantly reduces voltage stress on transistor gate oxides is disclosed. The charge pump circuit according to a preferred embodiment of the present invention includes circuitry that biases the otherwise vulnerable transistors in the charge pump circuit such that the voltage across their gate oxide is reduced. The charge pump of the present invention further provides circuitry to reduce leakage current.

摘要翻译： 公开了改进的电荷泵电路，其显着降低晶体管栅极氧化物上的电压应力。 根据本发明的优选实施例的电荷泵电路包括电路，其偏置电荷泵电路中的其它脆弱的晶体管，使得其栅极氧化物两端的电压降低。 本发明的电荷泵还提供减少泄漏电流的电路。

公开(公告)号：US07196542B1

公开(公告)日：2007-03-27

申请号：US10977332

申请日：2004-10-28

申请人： Andy Lee ,  Toan Nguyen ,  Stephanie Tran ,  Cameron McClintock ,  Brian Johnson

发明人： Andy Lee ,  Toan Nguyen ,  Stephanie Tran ,  Cameron McClintock ,  Brian Johnson

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/17788

摘要： Techniques are provided for increasing flexibility to I/O banks with respect to supply voltages. Multiple supply voltages can be provided to a bank of I/O pins. Separate I/O pins residing in an I/O bank are driven by buffers that are coupled to different supply voltages. Dedicated I/O pins are driven by buffers with pre-selected supply voltages. The dedicated I/O pins can be grouped together into the same I/O bank providing greater flexibility to drive signals on I/O pins in other I/O banks at different voltages. Also, a dual mode input buffer can drive an input signal to a voltage determined by one of two possible supply voltage levels. In addition, power on reset circuits for an I/O bank can monitor the voltage of two or more supply voltages.

摘要翻译： 提供了相对于电源电压提高I / O组的灵活性的技术。 可以向一组I / O引脚提供多个电源电压。 驻留在I / O组中的单独I / O引脚由耦合到不同电源电压的缓冲器驱动。 专用I / O引脚由具有预选电源电压的缓冲器驱动。 专用I / O引脚可以组合在同一个I / O bank中，提供更大的灵活性，以在不同电压的其他I / O bank中的I / O引脚上驱动信号。 此外，双模式输入缓冲器可以将输入信号驱动到由两个可能的电源电压电平之一确定的电压。 此外，I / O bank的上电复位电路可以监视两个或多个电源电压的电压。

公开(公告)号：US06774707B1

公开(公告)日：2004-08-10

申请号：US10050004

申请日：2002-01-14

申请人： Mian Smith ,  Myron Wong ,  Guu Lin ,  Stephanie Tran

发明人： Mian Smith ,  Myron Wong ,  Guu Lin ,  Stephanie Tran

IPC分类号： G05F110

CPC分类号： H02M3/073

摘要： Charge pump circuits and methods of the present invention step up an input voltage to provide an output voltage. The charge pump circuits have one or more stages. Each stage may include a capacitor and a transistor. Each stage adds an incremental voltage to an input voltage. The capacitors elevate the voltage at a terminal of the transistors in each stage in response to a clock signal to provide the incremental voltage. The output voltage is the sum of the input voltage and the incremental voltages provided by each stage. One or more of the stages of the charge pump circuit may have a depletion transistor. Depletion transistors may be field-effect transistors that have a lower threshold voltage as a result of an implant in the channel region of the device.

摘要翻译： 本发明的电荷泵电路和方法升高输入电压以提供输出电压。 电荷泵电路具有一个或多个阶段。 每个级可以包括电容器和晶体管。 每个阶段向输入电压增加一个增量电压。 电容器响应于时钟信号提升每级晶体管端子处的电压，以提供增量电压。 输出电压是输入电压和每级提供的增量电压之和。 电荷泵电路的一个或多个阶段可以具有耗尽晶体管。 耗尽晶体管可以是由于在器件的沟道区域中的注入而具有较低阈值电压的场效应晶体管。

公开(公告)号：US07161384B1

公开(公告)日：2007-01-09

申请号：US11180069

申请日：2005-07-12

申请人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

发明人： Guu Lin ,  Stephanie Tran ,  Bruce Pederson ,  Brad Vest ,  Jim Park ,  Jay Schleicher

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

摘要翻译： 用于新的路由结构和方法的方法和装置，其改善了用户定义的功能对可编程逻辑设备的拟合。 特别是第二次装配得到改善。 示例性结构和方法包括通过提供多个扩展和旁路路径允许使用来自多于一个相邻宏小区的输入扩展产品术语。 此外，产品术语“或”移位可防止宏单元输出级被掩埋并使其不可访问，并且在扩展器字线上提供宏单元输出，提高这些线路的效率以及节省路由资源。 扩展，旁路，或移位和扩展器字线可以以逻辑阵列块边界终止，或者可以超出这些边界到其他逻辑阵列块。

公开(公告)号：US20050270714A1

公开(公告)日：2005-12-08

申请号：US10861604

申请日：2004-06-03

申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。