公开(公告)号：US20050270714A1

公开(公告)日：2005-12-08

申请号：US10861604

申请日：2004-06-03

申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

公开(公告)号：US20070279817A1

公开(公告)日：2007-12-06

申请号：US11890933

申请日：2007-08-07

申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie Tran

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

公开(公告)号：US07400480B2

公开(公告)日：2008-07-15

申请号：US11890933

申请日：2007-08-07

申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

IPC分类号： H02H3/22

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。

公开(公告)号：US07271989B2

公开(公告)日：2007-09-18

申请号：US10861604

申请日：2004-06-03

申请人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

发明人： Cheng-Hsiung Huang ,  Guu Lin ,  Shih-Lin S. Lee ,  Chih-Ching Shih ,  Irfan Rahim ,  Stephanie T. Tran

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0251

摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.

公开(公告)号：US07250660B1

公开(公告)日：2007-07-31

申请号：US10891988

申请日：2004-07-14

申请人： Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Jeffrey Tyhach ,  Guu Lin ,  Chiakang Sung ,  Stephanie T. Tran

发明人： Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Jeffrey Tyhach ,  Guu Lin ,  Chiakang Sung ,  Stephanie T. Tran

IPC分类号： H01L23/62 ,  H01L29/72 ,  H01L29/73 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L27/0266

摘要： Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.

摘要翻译： 描述了为支持低电压差分信号（LVDS）和片上终止（OCT）标准的I / O电路提供静电放电保护的电路。 在I / O晶体管上连接至少一个附加晶体管。 在LVDS的情况下，使用一对堆叠的晶体管，其中源/漏区和阱抽头之间的距离对于连接到I / O焊盘的晶体管相当大。 PMOS晶体管和NMOS晶体管也可以串联连接在诸如电源节点的第一节点和I / O焊盘之间。 还公开了一种OCT电路，其中源极/漏极区域和OCT晶体管中的阱阱之间的间隔小于I / O晶体管中的间距。

公开(公告)号：US08704313B1

公开(公告)日：2014-04-22

申请号：US11406694

申请日：2006-04-18

申请人： Irfan Rahim ,  Cheng-Hsiung Huang

发明人： Irfan Rahim ,  Cheng-Hsiung Huang

IPC分类号： H01L29/78

CPC分类号： H01L29/7391 ,  H01L27/0255

摘要： An electrostatic discharge (ESD) protection structure comprising a polysilicon gate on an insulating layer on a substrate, said gate having first and second sides, a first heavily doped P-region in the substrate on the first side of the gate, a first heavily doped N-region in the substrate on the second side of the gate, and a shallow trench isolation isolating said first P-region and said first N-region from other structures in the substrate. In a first embodiment, the heavily doped regions are formed in a well having opposite conductivity to that of the substrate and a diode is formed at a PN junction between one of the heavily doped regions and the well. To minimize capacitance between the well and the substrate, the substrate is doped at a level of native doping and the well is isolated so that no other wells or heavily-doped regions are nearby in the substrate. Doping levels in the well and the dimensions of the gate are controlled to minimize on resistance (Ron) of the diode. In a second embodiment, no well is used.

摘要翻译： 一种静电放电（ESD）保护结构，包括在衬底上的绝缘层上的多晶硅栅极，所述栅极具有第一和第二侧，栅极第一侧上的衬底中的第一重掺杂P区，第一重掺杂 在栅极的第二侧的衬底中的N区，以及将衬底中的其它结构隔离所述第一P区和所述第一N区的浅沟槽隔离。 在第一实施例中，重掺杂区域形成在具有与衬底相反的导电性的阱中，并且在重掺杂区域之一和阱之间的PN结处形成二极管。 为了最小化阱和衬底之间的电容，衬底以天然掺杂的水平掺杂，并且阱被隔离，使得衬底中没有其它阱或重掺杂区域在附近。 阱中的掺杂电平和栅极的尺寸被控制以使二极管的导通电阻（Ron）最小化。 在第二实施例中，不使用井。

公开(公告)号：US07955923B1

公开(公告)日：2011-06-07

申请号：US12845337

申请日：2010-07-28

申请人： Antonio Gallerano ,  Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Jeffrey T. Watt

发明人： Antonio Gallerano ,  Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Jeffrey T. Watt

IPC分类号： H01L21/8238

CPC分类号： H01L29/6659 ,  H01L27/0277 ,  H01L29/1083 ,  H01L29/1087 ,  H01L2924/14

摘要： A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors. In these embodiments, either an N+/PLDD diode or an implanted diode is formed in place of one of the transistors.

摘要翻译： 通过在I / O焊盘和下拉装置的主体之间连接二极管，为下拉装置提供触发电路。 在一个实施例中，下拉装置形成为单个阱中的多个分立晶体管。 每个晶体管的漏极通过镇流电阻连接到I / O焊盘; 并且每个晶体管的源极通过镇流电阻器连接到地。 触发电路是形成在与晶体管不同的阱中的二极管。 二极管的阴极连接到I / O焊盘，阳极通过位于晶体管之间的中心抽头连接到晶体管。 优选地，晶体管是形成在P阱中的NMOS晶体管。 有利地，二极管是N + / PLDD二极管。 或者，二极管是N + / P二极管，其中P区由ESD注入形成。 在其他实施例中，二极管形成在与晶体管相同的阱中。 在这些实施例中，形成N + / PLDD二极管或注入二极管代替晶体管之一。

公开(公告)号：US07511533B1

公开(公告)日：2009-03-31

申请号：US11364779

申请日：2006-02-27

申请人： Hugh Sungki O ,  Chih-Ching Shih ,  Cheng-Hsiung Huang ,  Yow-Juang Bill Liu

发明人： Hugh Sungki O ,  Chih-Ching Shih ,  Cheng-Hsiung Huang ,  Yow-Juang Bill Liu

IPC分类号： H03K19/0175

CPC分类号： H03K19/01721

摘要： Circuits, methods, and apparatus for output devices having parasitic transistors for a higher output current drive. One such MOS output device includes a parasitic bipolar transistor that assists output voltage transitions. The parasitic transistor may be inherent in the structure of the MOS device. Alternately, one or more regions, such as implanted or diffused regions, may be added to the MOS device to form or enhance the parasitic bipolar device. The parasitic transistor is turned on when during an appropriate output transition and turned off once the transition is complete. The parasitic device may be turned on by injecting current into the bulk of a pull-down device, by pulling current out of the bulk of a pull-up device, or by tying the bulk of the output device to an appropriate voltage, such as VCC for a pull-down device or ground for a pull-up device.

摘要翻译： 具有用于较高输出电流驱动的寄生晶体管的输出装置的电路，方法和装置。 一个这样的MOS输出装置包括辅助输出电压转换的寄生双极晶体管。 寄生晶体管可以是MOS器件的结构中固有的。 或者，可以将一个或多个区域（例如注入或扩散区域）添加到MOS器件中以形成或增强寄生双极器件。 寄生晶体管在适当的输出转换期间导通，一旦转换完成，该寄生晶体管就会断开。 寄生器件可以通过将电流注入下拉器件的体积中，通过将电流从上拉器件的主体中拉出，或者通过将输出器件的大部分绑定到适当的电压，例如 用于下拉器件的VCC或用于上拉器件的接地。

公开(公告)号：US07471493B1

公开(公告)日：2008-12-30

申请号：US11365070

申请日：2006-02-28

申请人： Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Hugh Sung-Ki O ,  Yowjuang (Bill) Liu

发明人： Cheng-Hsiung Huang ,  Chih-Ching Shih ,  Hugh Sung-Ki O ,  Yowjuang (Bill) Liu

IPC分类号： H02H9/00 ,  H02H1/00

CPC分类号： H01L27/0262 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A pair of SCR devices connected in antiparallel between first and second nodes. Each SCR device comprises an NPN and a PNP bipolar transistor. Reverse-biased Zener diodes are used for triggering the NPN bipolar transistor in each SCR device when it breaks down in an ESD event. Advantageously, additional Zener diodes are provided for pre-charging the PNP transistor of each SCR device at the same time, thereby reducing the delay time for turning on the PNP bipolar transistor. In addition, the breakdown current of the Zener diodes is preferably maximized by reducing the P-well and N-well resistance of the SCRs. This is achieved by connecting external resistances between the base of each bipolar transistor and the node to which the emitter of the transistor is connected.

摘要翻译： 在第一和第二节点之间反并联连接的一对SCR设备。 每个SCR器件包括NPN和PNP双极晶体管。 反向偏置齐纳二极管用于在ESD事件中发生故障时触发每个SCR器件中的NPN双极晶体管。 有利地，提供了额外的齐纳二极管，用于同时为每个SCR器件的PNP晶体管预充电，从而减少了导通PNP双极晶体管的延迟时间。 此外，通过降低SCR的P阱和N阱电阻，优选使齐纳二极管的击穿电流最大化。 这是通过连接每个双极晶体管的基极与晶体管的发射极连接的节点之间的外部电阻来实现的。

公开(公告)号：US07408754B1

公开(公告)日：2008-08-05

申请号：US10992591

申请日：2004-11-18

申请人： Hugh Sung-Ki O ,  Chih-Ching Shih ,  Yow-Juang Bill Liu ,  Cheng-Hsiung Huang ,  Wei-Guang Wu ,  Billy Jow-Tai Kwong ,  Yu-Cheng Richard Gao

发明人： Hugh Sung-Ki O ,  Chih-Ching Shih ,  Yow-Juang Bill Liu ,  Cheng-Hsiung Huang ,  Wei-Guang Wu ,  Billy Jow-Tai Kwong ,  Yu-Cheng Richard Gao

IPC分类号： H02H3/20

CPC分类号： H01L27/0262

摘要： The present invention provides an ESD device for protecting thin oxide layers in transistors or capacitors in an integrated circuit. In one embodiment, the ESD device includes a silicon-controlled rectifier (SCR), the SCR including a PNP bipolar transistor and a NPN bipolar transistor. The ESD device further includes first and second trigger devices coupled to the SCR and configured to simultaneously turn on the PNP bipolar transistor and the NPN bipolar transistor in response to an ESD pulse on the ESD device. The base of the NPN bipolar transistor is floating to allow a first external resistor to be connected between the base and emitter of the NPN bipolar transistor. A second external resistor can be connected between the base and emitter of the PNP bipolar transistor.

摘要翻译： 本发明提供一种用于在集成电路中保护晶体管或电容器中的薄氧化物层的ESD装置。 在一个实施例中，ESD器件包括硅控整流器（SCR），SCR包括PNP双极晶体管和NPN双极晶体管。 ESD器件还包括耦合到SCR的第一和第二触发器件，并被配置为响应于ESD器件上的ESD脉冲同时导通PNP双极晶体管和NPN双极晶体管。 NPN双极晶体管的基极是浮置的，以允许第一外部电阻器连接在NPN双极晶体管的基极和发射极之间。 第二个外部电阻可以连接在PNP双极晶体管的基极和发射极之间。