-
公开(公告)号：US20050270714A1
公开(公告)日：2005-12-08
申请号：US10861604
申请日：2004-06-03
申请人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin Lee , Chih-Ching Shih , Irfan Rahim , Stephanie Tran
发明人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin Lee , Chih-Ching Shih , Irfan Rahim , Stephanie Tran
CPC分类号： H01L27/0266 , H01L27/0251
摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。
-
公开(公告)号：US20070279817A1
公开(公告)日：2007-12-06
申请号：US11890933
申请日：2007-08-07
申请人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin Lee , Chih-Ching Shih , Irfan Rahim , Stephanie Tran
发明人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin Lee , Chih-Ching Shih , Irfan Rahim , Stephanie Tran
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L27/0251
摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。
-
公开(公告)号：US07400480B2
公开(公告)日：2008-07-15
申请号：US11890933
申请日：2007-08-07
申请人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
发明人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
IPC分类号： H02H3/22
CPC分类号： H01L27/0266 , H01L27/0251
摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
摘要翻译： 提供具有诸如可编程多晶硅保险丝等敏感电路的集成电路。 提供静电放电（ESD）保护电路，防止在存在静电放电事件时敏感电路的损坏或不期望的编程。 静电放电保护电路可以具有电源ESD器件，其将敏感电路两端的电压电平限制到最大电压，并且当暴露于ESD信号时，其将电流从敏感电路吸取。 静电放电保护电路还可以具有ESD余量电路，当在敏感电路上施加最大电压时，该余量电路有助于防止电流流经敏感电路。
-
公开(公告)号：US07271989B2
公开(公告)日：2007-09-18
申请号：US10861604
申请日：2004-06-03
申请人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
发明人： Cheng-Hsiung Huang , Guu Lin , Shih-Lin S. Lee , Chih-Ching Shih , Irfan Rahim , Stephanie T. Tran
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L27/0251
摘要： Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
-
公开(公告)号：US07250660B1
公开(公告)日：2007-07-31
申请号：US10891988
申请日：2004-07-14
申请人： Cheng-Hsiung Huang , Chih-Ching Shih , Jeffrey Tyhach , Guu Lin , Chiakang Sung , Stephanie T. Tran
发明人： Cheng-Hsiung Huang , Chih-Ching Shih , Jeffrey Tyhach , Guu Lin , Chiakang Sung , Stephanie T. Tran
IPC分类号： H01L23/62 , H01L29/72 , H01L29/73 , H01L29/74 , H01L31/111
CPC分类号： H01L27/0266
摘要： Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.
摘要翻译： 描述了为支持低电压差分信号（LVDS）和片上终止（OCT）标准的I / O电路提供静电放电保护的电路。 在I / O晶体管上连接至少一个附加晶体管。 在LVDS的情况下，使用一对堆叠的晶体管，其中源/漏区和阱抽头之间的距离对于连接到I / O焊盘的晶体管相当大。 PMOS晶体管和NMOS晶体管也可以串联连接在诸如电源节点的第一节点和I / O焊盘之间。 还公开了一种OCT电路，其中源极/漏极区域和OCT晶体管中的阱阱之间的间隔小于I / O晶体管中的间距。
-
公开(公告)号：US07981753B1
公开(公告)日：2011-07-19
申请号：US12683402
申请日：2010-01-06
IPC分类号： H01L21/331
CPC分类号： H01L27/0266 , H01L21/265 , H01L29/0692 , H01L29/41775 , H01L29/456 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.
摘要翻译： 提供了一种用于提供静电放电（ESD）保护的装置。 该器件包括其中形成有漏极，源极和栅极的半导体衬底。 漏极包含具有比漏极和源极的其余部分的电阻高的电阻的区域。 栅极区域与该较高电阻区域和源极接触。 在一个实施例中，为了提供更高的电阻，较高的电阻缺少硅化物。 包括形成用于提供ESD保护的装置的方法。
-
公开(公告)号：US07821050B1
公开(公告)日：2010-10-26
申请号：US11497017
申请日：2006-07-31
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/118 , G11C5/005 , G11C11/4125 , H01L27/11 , H01L27/1104 , H01L29/4983 , H01L29/66659 , Y10S257/903
摘要： A transistor fabricated on a semiconductor substrate includes a source and a drain in the substrate; a gate on the substrate, the gate being insulated from the substrate by gate dielectric; barrier layers covering two sides of the gate and the gate dielectric; spacers of high-k material covering the barrier layers; and nitride spacers covering the spacers of high-k material. The spacers of high-k material significantly increase the node capacitance of the transistor and therefore reduce the transistor's soft error rate.
摘要翻译： 制造在半导体衬底上的晶体管包括衬底中的源极和漏极; 基板上的栅极，栅极通过栅极电介质与基板绝缘; 覆盖栅极和栅极电介质的两侧的阻挡层; 覆盖阻挡层的高k材料的间隔物; 以及覆盖高k材料的间隔物的氮化物间隔物。 高k材料的间隔物显着增加了晶体管的节点电容，从而降低了晶体管的软错误率。
-
公开(公告)号：US20070002507A1
公开(公告)日：2007-01-04
申请号：US11173254
申请日：2005-07-01
申请人： Hugh O , Chih-Ching Shih , Cheng-Hsiung Huang , Yow-Juang Liu
发明人： Hugh O , Chih-Ching Shih , Cheng-Hsiung Huang , Yow-Juang Liu
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.
摘要翻译： ESD器件发明包括形成在衬底中的第一和第二晶体管，每个具有源极，漏极和栅极，第一事务的源极和漏极连接在地和I / O引脚或输入之间， 第一晶体管连接到地，并且第二晶体管的源极和漏极连接在第一晶体管的衬底和I / O引脚或输入之间; 在地和I / O引脚或输入之间串联连接的第一和第二电容器; 以及至少第三晶体管，其连接在第一和第二电容器之间的接地和节点之间，第二晶体管的栅极也连接到该节点。
-
公开(公告)号：US07808047B1
公开(公告)日：2010-10-05
申请号：US11897915
申请日：2007-08-31
IPC分类号： H01L23/62
CPC分类号： H01L29/6659 , H01L27/0277 , H01L29/1083 , H01L29/1087 , H01L2924/14
摘要： A trigger circuit is provided for a pull-down device by connecting a diode between the I/O pad and the body of the pull-down device. In one embodiment, the pull-down device is formed as a plurality of discrete transistors in a single well. The drain of each transistor is connected through a ballast resistor to the I/O pad; and the source of each transistor is connected through a ballast resistor to ground. The trigger circuit is a diode formed in a different well from that of the transistors. The cathode of the diode is connected to the I/O pad and the anode is connected to the transistor well through a center tap located between the transistors. Preferably, the transistors are NMOS transistors formed in a P-well. Advantageously, the diode is an N+/PLDD diode. Alternatively, the diode is an N+/P diode where the P region is formed by an ESD implant. In other embodiments the diode is formed in the same well as the transistors. In these embodiments, either an N+/PLDD diode or an implanted diode is formed in place of one of the transistors.
摘要翻译： 通过在I / O焊盘和下拉装置的主体之间连接二极管，为下拉装置提供触发电路。 在一个实施例中，下拉装置形成为单个阱中的多个分立晶体管。 每个晶体管的漏极通过镇流电阻连接到I / O焊盘; 并且每个晶体管的源极通过镇流电阻器连接到地。 触发电路是形成在与晶体管不同的阱中的二极管。 二极管的阴极连接到I / O焊盘，阳极通过位于晶体管之间的中心抽头连接到晶体管。 优选地，晶体管是形成在P阱中的NMOS晶体管。 有利地，二极管是N + / PLDD二极管。 或者，二极管是N + / P二极管，其中P区由ESD注入形成。 在其他实施例中，二极管形成在与晶体管相同的阱中。 在这些实施例中，形成N + / PLDD二极管或注入二极管代替晶体管之一。
-
公开(公告)号：US07671416B1
公开(公告)日：2010-03-02
申请号：US10956758
申请日：2004-09-30
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L21/265 , H01L29/0692 , H01L29/41775 , H01L29/456 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.
摘要翻译： 提供了一种用于提供静电放电（ESD）保护的装置。 该器件包括其中形成有漏极，源极和栅极的半导体衬底。 漏极包含具有比漏极和源极的其余部分的电阻高的电阻的区域。 栅极区域与该较高电阻区域和源极接触。 在一个实施例中，为了提供更高的电阻，较高的电阻缺少硅化物。 包括形成用于提供ESD保护的装置的方法。
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.028 秒)
