公开(公告)号：US09910454B2

公开(公告)日：2018-03-06

申请号：US13490729

申请日：2012-06-07

申请人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

发明人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

IPC分类号： H04L7/00 ,  G06F1/12 ,  H04J3/06

CPC分类号： G06F1/12 ,  H04J3/0697

摘要： Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

公开(公告)号：US20130329842A1

公开(公告)日：2013-12-12

申请号：US13490729

申请日：2012-06-07

申请人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

发明人： William John Bainbridge ,  Stephen W. Hamilton ,  Neal T. Wingen

IPC分类号： H04L7/00

CPC分类号： G06F1/12 ,  H04J3/0697

摘要： Data payload is passed over a boundary from a sender module (SM) on one side of the boundary to a receiver module (RM) on the other side of the boundary. The SM has two or more multiplexers to pass the data payload over to a receiver storage register in the RM. Each multiplexer has 1) its own read address pointer lane coming from sequencing logic located on the RM side and 2) data slots to send data payload from that multiplexer across the boundary to the receiver storage register in the RM in a qualified event synchronization. The sequencing logic ensures that the multiple read address pointers going to the multiplexers have a fixed alternating relationship amongst themselves; and thus, the multiple read address pointers syncopate between each other to move the data payload across the boundary to provide 100% throughput.

摘要翻译： 数据有效载荷从边界一侧的发送器模块（SM）到边界另一侧的接收器模块（RM）通过边界传递。 SM具有两个或多个多路复用器，以将数据有效载荷传递到RM中的接收器存储寄存器。 每个复用器具有1）来自位于RM侧的排序逻辑的自己的读地址指针通道，以及2）数据时隙，以在合格事件同步中将数据有效载荷从跨越边界的多路复用器发送到RM中的接收器存储寄存器。 排序逻辑确保去往多路复用器的多个读地址指针在它们之间具有固定的交替关系; 并且因此，多个读取地址指针彼此之间相互重合以跨越边界移动数据有效载荷以提供100％的吞吐量。

公开(公告)号：US20130073878A1

公开(公告)日：2013-03-21

申请号：US13434605

申请日：2012-03-29

申请人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

发明人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

摘要： An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.

摘要翻译： 互连功率管理器（IPM）与集成电路中的集成电路系统功率管理器（SPM）协作并传送信号。 互连网络（IN）被划分成多个电力域，并且当IN中的事务的路由路径跨越一个或多个电力时，将集成到IN中的硬件电路集成到IN中的每个电力域中的所有组件的静态状态 域内的边界，并导致IN内的电源域的相互依赖关系，而不是发起方代理的权力域和交易的最终目标代理所在的地方。 SPM被配置为与IPM协作和通信以静默，唤醒以及IN内的多个电力域中的两个，一个或多个的任何组合。

公开(公告)号：US07243264B2

公开(公告)日：2007-07-10

申请号：US10285987

申请日：2002-11-01

申请人： Wolf-Dietrich Weber ,  Chien-Chun Chou ,  Jeffrey Allen Ebert ,  Stephen W. Hamilton ,  Michael J. Meyer

发明人： Wolf-Dietrich Weber ,  Chien-Chun Chou ,  Jeffrey Allen Ebert ,  Stephen W. Hamilton ,  Michael J. Meyer

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0757 ,  H04L69/40

摘要： A method and apparatus for error handling in networks have been described. The method configures a plurality of cores, wherein each core is connected with and associated with each of one of a plurality of initiators. The method further connects one or more of the initiators to a network. Next, one or more of the initiators determine an error in one or more of the cores and communicate the error.

摘要翻译： 已经描述了用于网络中的错误处理的方法和装置。 该方法配置多个核心，其中每个核心与多个启动器中的一个启动器中的每一个连接并与之相关联。 该方法还将一个或多个启动器连接到网络。 接下来，一个或多个启动器确定一个或多个核心中的错误并传达错误。

公开(公告)号：US5450455A

公开(公告)日：1995-09-12

申请号：US84039

申请日：1993-06-28

申请人： Stephen W. Hamilton ,  Walter E. Gibson ,  Cheng-Gang Kong

发明人： Stephen W. Hamilton ,  Walter E. Gibson ,  Cheng-Gang Kong

IPC分类号： G06F11/22 ,  G01R31/3185 ,  H04B3/46

CPC分类号： G01R31/318586

摘要： A scannable logic unit includes one or more storage registers that maintain copies of data communicated from the scannable unit to registers in a nonscannable unit. When the scannable unit is subjected to a scan test, the registers will contain state information respecting that transfer to the nonscannable unit. When the scannable and nonscannable units are placed in a run condition, the registers supply to the nonscannable unit state information for continuing operation.

摘要翻译： 可扫描逻辑单元包括一个或多个存储寄存器，其将从可扫描单元传送的数据的副本维护到非可更新单元中的寄存器。 当可扫描单元进行扫描测试时，寄存器将包含关于转移到不可更改单元的状态信息。 当可扫描和不可取消单元处于运行状态时，寄存器提供用于继续操作的非可修改单元状态信息。

公开(公告)号：US08868941B2

公开(公告)日：2014-10-21

申请号：US13434605

申请日：2012-03-29

申请人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

发明人： Doddaballapur N. Jayasimha ,  Drew E. Wingard ,  Stephen W. Hamilton

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06G7/54 ,  G06F13/00 ,  G06F15/00

CPC分类号： G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

摘要： An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.

摘要翻译： 互连功率管理器（IPM）与集成电路中的集成电路系统功率管理器（SPM）协作并传送信号。 互连网络（IN）被划分成多个电力域，并且当IN中的事务的路由路径跨越一个或多个电力时，将集成到IN中的硬件电路集成到IN中的每个电力域中的所有组件的静态状态 域内的边界，并导致IN内的电源域的相互依赖关系，而不是发起方代理的权力域和交易的最终目标代理所在的地方。 SPM被配置为与IPM协作和通信以静默，唤醒以及IN内的多个电力域中的两个，一个或多个的任何组合。

公开(公告)号：US08407433B2

公开(公告)日：2013-03-26

申请号：US12144883

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

摘要翻译： 在一个实施例中，用于集成电路的互连传送一个或多个启动器知识产权（IP）核与耦合到互连的多个目标IP核之间的事务。 两个或多个内存通道组成目标IP内核的第一个聚合目标。 两个或多个内存通道填充分配给第一个聚合目标的地址空间，并显示为发起者IP内核的单个目标。 互连实现斩波逻辑以将从第一存储器通道的存储器通道地址边界跨越第一聚合目标内的第二存储器通道的单独的二维（2D）事务转换为具有大于1的高度值的两个或更多个2D事务 ，以及步长和宽度尺寸，其被切碎以适合于第一聚集目标的存储器通道地址边界。

公开(公告)号：US20120036296A1

公开(公告)日：2012-02-09

申请号：US13276041

申请日：2011-10-18

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F13/42

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect. The flow control logic for the interconnect applies a flow control splitting protocol to permit transactions from each initiator thread and/or each initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual targets within an aggregate target at once. The combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in an aggregate target from the same thread or tag at the same time.

摘要翻译： 描述了一种方法，装置和系统，其通常涉及具有互连的集成电路。 用于互连的流控制逻辑应用流控制分割协议，以允许来自每个发起者线程和/或每个发起者标签流的事务一次对单个聚合目标中的多个信道而言是突出的，并且因此对于聚合中的多个单个目标 一目了然 组合的流控制逻辑和流控制协议允许互连同时管理来自相同线程或标签的聚合目标中的多个信道的同时请求。

公开(公告)号：US08032329B2

公开(公告)日：2011-10-04

申请号：US12204156

申请日：2008-09-04

申请人： Chien-Chun Chou ,  Stephen W. Hamilton ,  Drew E. Wingard ,  Pascal Chauvet

发明人： Chien-Chun Chou ,  Stephen W. Hamilton ,  Drew E. Wingard ,  Pascal Chauvet

IPC分类号： G06F11/30 ,  G06F9/44 ,  G06F9/45

CPC分类号： G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/87 ,  G06F2201/88

摘要： Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A performance monitoring apparatus may be located on an interconnect of a fabricated integrated circuit. An event measurement module (EM) includes an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator intellectual property (IP) cores and target IP cores over the interconnect. The EM further includes a software visible register block that provides software access for controlling the EM on which one or more transactions to monitor and to configure one or more parameters associated with that transaction to track. The EM further includes a filtering sub-module that selects transactions to be monitored based on information received from the software. The performance counter module aggregates events and event measurements received from the EM into quantities of performance metrics associated with transactions between the IP cores over the interconnect.

摘要翻译： 描述了提供电子设计的仪器和分析的各种方法和装置。 性能监视装置可以位于所制造的集成电路的互连上。 事件测量模块（EM）包括一个事件发生器子模块，该事件发生器子模块通过互连产生与发起者知识产权（IP）核心和目标IP内核之间的事务相关联的监视事件和事件测量。 EM还包括软件可见寄存器块，其提供用于控制EM监视的一个或多个事务的软件访问以及配置与该事务相关联的一个或多个参数以进行跟踪。 EM还包括一个过滤子模块，该过滤子模块根据从软件接收的信息来选择要监视的事务。 性能计数器模块将从EM接收到的事件和事件测量聚合到与互连上的IP内核之间的事务相关联的性能度量数量。

公开(公告)号：US20080320255A1

公开(公告)日：2008-12-25

申请号：US12145257

申请日：2008-06-24

申请人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

发明人： Drew E. Wingard ,  Chien-Chun Chou ,  Stephen W. Hamilton ,  Ian Andrew Swarbrick ,  Vida Vakilotojar

IPC分类号： G06F12/02

CPC分类号： G11C7/1072 ,  G06F12/0607 ,  G06F15/17375 ,  Y02D10/13

摘要： An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

摘要翻译： 通常描述用于传送发起者知识产权（IP）核心和耦合到互连的多个目标IP核之间的事务的集成电路的互连。 互连路由集成电路中的目标IP内核和启动器IP内核之间的事务。 目标IP核的第一聚合目标包括在地址映射中的第一聚合目标的地址空间中交错的两个或更多个存储器通道。 每个存储器通道在定义的存储器交错段中分割，然后与来自其他存储器通道的存储器交错段进行交织。 地址图分为两个或更多个区域。 每个交错存储器交错段被分配给这些区域中的至少一个并填充该区域的地址空间，并且与区域和存储器交错段相关联的参数是可配置的。