-
公开(公告)号：US08508974B2
公开(公告)日：2013-08-13
申请号：US13240420
申请日：2011-09-22
CPC分类号： G11C11/2253 , G11C11/2275
摘要： A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.
摘要翻译： 铁电存储器件包括分配开关，其被配置为使铁电存储器件的铁电电容器的两侧短路。 因此，分流开关被配置为在从铁电电容器读取数据之前或之后从铁电电容器周围除去多余的电荷。 通过一种方法，分流开关被连接以对来自控制接入铁电电容器的相同线路的信号进行操作。 这样配置，例如通过施加预充电电压，通过消除用于否则从铁电电容器周围排出过量电荷的延迟来降低铁电存储器件的高性能周期时间。 分流开关还通过确保在读取周期期间过量的电荷不影响铁电电容器的读取来提高铁电存储器件的可靠性。
-
公开(公告)号：US20120170349A1
公开(公告)日：2012-07-05
申请号：US13240420
申请日：2011-09-22
IPC分类号： G11C11/22
CPC分类号： G11C11/2253 , G11C11/2275
摘要： A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.
摘要翻译： 铁电存储器件包括分配开关，其被配置为使铁电存储器件的铁电电容器的两侧短路。 因此，分流开关被配置为在从铁电电容器读取数据之前或之后从铁电电容器周围除去多余的电荷。 通过一种方法，分流开关被连接以对来自控制接入铁电电容器的相同线路的信号进行操作。 这样配置，例如通过施加预充电电压，通过消除用于否则从铁电电容器周围排出过量电荷的延迟来降低铁电存储器件的高性能周期时间。 分流开关还通过确保在读取周期期间过量的电荷不影响铁电电容器的读取来提高铁电存储器件的可靠性。
-
3.发明申请公开(公告)号：US20120170351A1
公开(公告)日：2012-07-05
申请号：US13243911
申请日：2011-09-23
IPC分类号： G11C11/22
CPC分类号： G11C11/1673 , G11C11/1677
摘要： An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).
摘要翻译： FRAM设备可以包括读出放大器和至少第一位单元。 第一位单元可以具有连接到读出放大器的位线和互补位线。 第一预充电电路在测试操作模式期间响应第一控制信号，以相对于第一电压对位线预充电，而在第二预充电电路期间第二预充电电路响应第二控制信号（与第一控制信号不同） 测试操作模式相对于不同于第一电压的测试电压（例如但不限于，例如大于地电压但小于第一电压的选择的测试电压）预充电补充位线 第一电压）。
-
公开(公告)号：US20120168837A1
公开(公告)日：2012-07-05
申请号：US13312352
申请日：2011-12-06
IPC分类号： H01L27/115 , H01L21/8246
CPC分类号： H01L27/11507 , H01L27/0207 , H01L27/11504 , H01L28/55
摘要： A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor.
摘要翻译： 铁电设备包括电路，该电路具有经由第一铁电电容器的顶端连接器电连接到板线的第一电容器和经由第一铁电电容器的底端连接而连接到存储节点的电路。 电路还包括经由第二铁电电容器的第二底部端子连接电耦合到第二板线的第二铁电电容器和经由第二铁电电容器的第二顶部端子连接到存储节点的第二铁电电容器。
-
公开(公告)号：US20120170348A1
公开(公告)日：2012-07-05
申请号：US13240252
申请日：2011-09-22
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.
摘要翻译： 自定时读出放大器读缓冲器拉低预充电的高全局位线，然后将数据馈送到直接连接到位线的三态回写缓冲器。 该位线向强电介质电容器充电以在绕过感测放大器和铁电电容器之间的隔离开关旁路时写入逻辑“1”或“0”。 由于读出放大器使用接地位线检测，所以读缓冲器不会开始下拉全局位线直到读出放大器信号放大，这使得该读缓冲器的控制信号的定时非关键。 回写缓冲器使能定时也是从读出放大器自定时的。 因此，读取到强电介质存储单元的数据被局部控制，并且在从铁电存储单元读取数据之后迅速开始，从而允许快速循环时间。
-
公开(公告)号：US08753952B2
公开(公告)日：2014-06-17
申请号：US13330833
申请日：2011-12-20
IPC分类号： H01L21/20
CPC分类号： H01L27/0805 , H01L27/0207 , H01L27/06 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L29/92
摘要： Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.
摘要翻译： 用于集成去耦电容器的铁电电容器结构等。 铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。 铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。 串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。
-
7.发明授权公开(公告)号：US08724367B2
公开(公告)日：2014-05-13
申请号：US13243875
申请日：2011-09-23
IPC分类号： G11C11/22
CPC分类号： G11C11/1673 , G11C11/1677 , G11C11/22 , G11C29/12 , G11C29/30 , G11C2029/1202 , G11C2029/5002
摘要： An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.
摘要翻译： FRAM设备可以包括读出放大器，至少第一位单元，第一控制线和第二控制线。 第一位单元可以具有通过第一隔离器和与第一隔离器不同的第二隔离器连接到读出放大器的互补位线连接到读出放大器的位线。 第一控制线可以连接到并控制上述第一隔离器。 并且第二控制线可以连接到并控制第二隔离器，使得第二隔离器相对于第一隔离器被独立地控制，以便于测试设备。
-
8.发明授权公开(公告)号：US08717800B2
公开(公告)日：2014-05-06
申请号：US13243911
申请日：2011-09-23
IPC分类号： G11C11/22
CPC分类号： G11C11/1673 , G11C11/1677
摘要： An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).
摘要翻译： FRAM设备可以包括读出放大器和至少第一位单元。 第一位单元可以具有连接到读出放大器的位线和互补位线。 第一预充电电路在测试操作模式期间响应第一控制信号，以相对于第一电压对位线预充电，而在第二预充电电路期间第二预充电电路响应第二控制信号（与第一控制信号不同） 测试操作模式相对于不同于第一电压的测试电压（例如但不限于，例如大于地电压但小于第一电压的选择的测试电压）预充电补充位线 第一电压）。
-
公开(公告)号：US08477522B2
公开(公告)日：2013-07-02
申请号：US13240252
申请日：2011-09-22
CPC分类号： G11C11/22
摘要： A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.
摘要翻译： 自定时读出放大器读缓冲器拉低预充电的高全局位线，然后将数据馈送到直接连接到位线的三态回写缓冲器。 该位线向强电介质电容器充电以在绕过感测放大器和铁电电容器之间的隔离开关旁路时写入逻辑“1”或“0”。 由于读出放大器使用接地位线检测，所以读缓冲器不会开始下拉全局位线直到读出放大器信号放大，这使得该读缓冲器的控制信号的定时非关键。 回写缓冲器使能定时也是从读出放大器自定时的。 因此，读取到强电介质存储单元的数据被局部控制，并且在从铁电存储单元读取数据之后迅速开始，从而允许快速循环时间。
-
公开(公告)号：US08441833B2
公开(公告)日：2013-05-14
申请号：US13445076
申请日：2012-04-12
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.021 秒)
