公开(公告)号：US09171940B2

公开(公告)日：2015-10-27

申请号：US13979253

申请日：2012-01-10

申请人： Sumio Katoh

发明人： Sumio Katoh

IPC分类号： H01L29/04 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786

CPC分类号： H01L29/66969 ,  H01L29/45 ,  H01L29/78606 ,  H01L29/78693

摘要： In a thin film transistor substrate (10) having an island-like channel protection layer (15a) covering a channel portion of an oxide semiconductor layer (14), a source electrode (16S) and a drain electrode (16D) are formed of an aluminum alloy film or a multilayer film including an aluminum alloy film.

摘要翻译： 在具有覆盖氧化物半导体层（14）的沟道部分的岛状沟道保护层（15a）的薄膜晶体管基板（10）中，源电极（16S）和漏电极（16D）由 铝合金膜或包含铝合金膜的多层膜。

公开(公告)号：US20130048998A1

公开(公告)日：2013-02-28

申请号：US13640354

申请日：2011-03-02

申请人： Sumio Katoh

发明人： Sumio Katoh

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  G02F1/1368 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device (ST) includes a substrate (11), a gate electrode (12b), a gate insulating film (13b), an oxide semiconductor film (14b) including a channel part (14bc) formed in a position facing the gate electrode (12b), a source electrode (15bs), and a drain electrode (15bd). The source electrode (15bs) and the drain electrode (15bd) is arranged so as not to overlap with the gate electrode (12b) as viewed in the plane. A region adjacent to the gate electrode (12b) and the source electrode (15bs) and a region adjacent to the gate electrode (12b) and the drain electrode (15bd) are, in a region where the source electrode (15bs) and the drain electrode (15bd) does not overlap with the gate electrode (12b), processed such that resistance in a region of the oxide semiconductor film (14b) including a surface thereof is reduced.

摘要翻译： 半导体器件（ST）包括衬底（11），栅极电极（12b），栅极绝缘膜（13b），氧化物半导体膜（14b），其包括形成在面对栅电极的位置的沟道部分 （12b），源极（15bs）和漏极（15bd）。 源极电极（15bs）和漏极电极（15bd）被布置成与平面中的栅电极（12b）不重叠。 与栅电极（12b）和源电极（15bs）相邻的区域和与栅电极（12b）和漏电极（15bd）相邻的区域在源电极（15bs）和漏极 电极（15bd）不与栅电极（12b）重叠，进行处理，使得包括其表面的氧化物半导体膜（14b）的区域中的电阻降低。

公开(公告)号：US20120241769A1

公开(公告)日：2012-09-27

申请号：US13511969

申请日：2010-07-16

申请人： Sumio Katoh

发明人： Sumio Katoh

IPC分类号： H01L31/105 ,  H01L31/18 ,  H01L27/146

CPC分类号： H01L31/101 ,  G02F1/13338 ,  G02F1/1368 ,  G02F2001/136245 ,  G02F2201/58 ,  H01L27/14632 ,  H01L27/14678 ,  H01L27/14692

摘要： A third semiconductor layer 14 is formed on a light receiving surface 13a of a second semiconductor layer 13 so as to cover the light receiving surface 13a of the second semiconductor layer 13 at least partially in a plan view. A first semiconductor layer 10 is formed on an opposite surface of the light receiving surface 13a of the second semiconductor layer 13 so as to overlap the light receiving surface 13a and the third semiconductor layer 14 at least partially in a plan view. In the second semiconductor layer 13, the relative light receiving sensitivity to respective wavelengths of light has the highest value at a wavelength in an infrared region. Thus, even if the intensity of light of the infrared region that is emitted to an object of detection is not increased when sensing by a photodiode is performed using light of the infrared range, it is possible to achieve a photodiode that has a high S/N ratio, which is a ratio of data of received light with respect to noise, and that has high detection accuracy.

摘要翻译： 第三半导体层14形成在第二半导体层13的光接收表面13a上，以至少部分平面地覆盖第二半导体层13的光接收表面13a。 第一半导体层10形成在第二半导体层13的光接收表面13a的相对表面上，以便以平面图至少部分地与光接收表面13a和第三半导体层14重叠。 在第二半导体层13中，相对于各波长的光的相对光接收灵敏度在红外区域的波长处具有最高值。 因此，即使利用红外线范围的光进行利用光电二极管的感测，发射到检测对象的红外线区域的光的强度也不会增加，所以可以实现高S / N比，其是接收光的数据相对于噪声的比率，并且具有高的检测精度。

公开(公告)号：US20120115286A1

公开(公告)日：2012-05-10

申请号：US13382448

申请日：2010-02-17

申请人： Tokuaki Kuniyoshi ,  Hidehito Kitakado ,  Tadayoshi Miyamoto ,  Kazuhide Tomiyasu ,  Sumio Katoh

发明人： Tokuaki Kuniyoshi ,  Hidehito Kitakado ,  Tadayoshi Miyamoto ,  Kazuhide Tomiyasu ,  Sumio Katoh

IPC分类号： H01L21/336

CPC分类号： H01L29/78621 ,  G02F1/1368 ,  H01L29/4908 ,  H01L29/66765

摘要： Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.

摘要翻译： 提供了一种薄膜晶体管制造方法，通过该方法可以制造具有LDD区的薄膜晶体管，而不增加所使用的光掩模的数量。 形成在TFT（10）的多晶硅膜（26）上的蚀刻停止层（35）不仅用作掩模以在通过蚀刻形成源电极和漏电极时保护沟道区（27） 而且当离子被注入以形成源/漏区（39）时也作为掩模。 因此，离子注入多晶硅膜（26）中以形成源极/漏极区（39）的磷未被植入LDD区（38）中，因此不需要另外形成 当植入离子时用作掩模的抗蚀剂图案。

公开(公告)号：US20140035478A1

公开(公告)日：2014-02-06

申请号：US14002211

申请日：2012-02-23

申请人： Hidehito Kitakado ,  Sumio Katoh

发明人： Hidehito Kitakado ,  Sumio Katoh

IPC分类号： H01L29/786 ,  H05B37/02 ,  H01L29/66

CPC分类号： H01L29/7869 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78618 ,  H05B37/02

摘要： The invention provides a thin film transistor having current driving force that can be substantially improved. By heat treatment, the IGZO layer (45) from which oxygen is taken away by the titanium electrodes (65) becomes the low resistance regions (40b), and the IGZO layer (45) from which oxygen is not taken away remains as the high resistance region (40a). In this state, when the gate voltage is applied to the gate electrode (20), electrons in the low resistance regions (40b) near the boundaries with the high resistance region (40a) move respectively to the titanium electrode (65) sides. As a result, the length of the low resistance regions (40b) becomes short, and oppositely, the length of the high resistance region (40a) becomes longer by the size of the shortened low resistance regions. However, the electrical channel length (Le) becomes shorter than the source/drain interval space (Lch) as the limit resolution of the exposure device, and the current driving force becomes large.

摘要翻译： 本发明提供一种薄膜晶体管，其具有可大大改善的电流驱动力。 通过热处理，由钛电极（65）夺取氧的IGZO层（45）成为低电阻区域（40b），并且不吸收氧气的IGZO层（45）保持为高 电阻区域（40a）。 在该状态下，当栅电极（20）施加栅极电压时，与高电阻区域（40a）的边界附近的低电阻区域（40b）中的电子分别移动到钛电极（65）侧。 结果，低电阻区域（40b）的长度变短，相反地，通过缩短的低电阻区域的尺寸，高电阻区域（40a）的长度变长。 然而，电通道长度（Le）比作为曝光装置的极限分辨率的源极/漏极间隔空间（Lch）短，并且电流驱动力变大。

公开(公告)号：US20130334530A1

公开(公告)日：2013-12-19

申请号：US14002794

申请日：2012-03-02

申请人： Sumio Katoh ,  Hidehito Kitakado

发明人： Sumio Katoh ,  Hidehito Kitakado

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78693 ,  H01L27/1222 ,  H01L29/41733 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L33/0041

摘要： The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.Widths of a source electrode (160a) and a drain electrode (160b) are smaller than a width of a channel layer (140). Accordingly, in the channel layer (140), low resistance regions (140b) are formed to surround respectively the source electrode (160a) and the drain electrode (160b). A high resistance region (140a) having a higher resistance value than those of the low resistance regions (140b) remains not only in the region sandwiched between the two low resistance regions (140b), but also in the end parts in the channel width direction. As a result, in a TFT (100), the high resistance region (140a) is extended not only to the channel region sandwiched between the source electrode (160a) and the drain electrode (160b), but also to the end parts in the channel width direction. Accordingly, the off-current flowing through the end parts in the channel width direction reduces.

摘要翻译： 本发明提供一种薄膜晶体管及其制造方法，该薄膜晶体管能够减小沟道层的沟道宽度方向的端部流过的截止电流。 源电极（160a）和漏电极（160b）的宽度小于沟道层（140）的宽度。 因此，在沟道层（140）中，分别形成有低电阻区域（140b）围绕源电极（160a）和漏电极（160b）。 具有比低电阻区域（140b）更高的电阻值的高电阻区域（140a）不仅保持在夹在两个低电阻区域（140b）之间的区域中，而且在通道宽度方向上的端部部分 。 结果，在TFT（100）中，高电阻区域（140a）不仅延伸到夹在源电极（160a）和漏电极（160b）之间的沟道区域，而且延伸到 通道宽度方向。 因此，在通道宽度方向流过端部的截止电流减少。

公开(公告)号：US08492212B2

公开(公告)日：2013-07-23

申请号：US13382448

申请日：2010-02-17

申请人： Tokuaki Kuniyoshi ,  Hidehito Kitakado ,  Tadayoshi Miyamoto ,  Kazuhide Tomiyasu ,  Sumio Katoh

发明人： Tokuaki Kuniyoshi ,  Hidehito Kitakado ,  Tadayoshi Miyamoto ,  Kazuhide Tomiyasu ,  Sumio Katoh

IPC分类号： H01L29/66765

CPC分类号： H01L29/78621 ,  G02F1/1368 ,  H01L29/4908 ,  H01L29/66765

摘要： Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.

摘要翻译： 提供了一种薄膜晶体管制造方法，通过该方法可以制造具有LDD区的薄膜晶体管，而不增加所使用的光掩模的数量。 形成在TFT（10）的多晶硅膜（26）上的蚀刻停止层（35）不仅用作掩模以在通过蚀刻形成源电极和漏电极时保护沟道区（27） 而且当离子被注入以形成源/漏区（39）时也作为掩模。 因此，离子注入多晶硅膜（26）中以形成源极/漏极区（39）的磷未被植入LDD区（38）中，因此不需要另外形成 当植入离子时用作掩模的抗蚀剂图案。

公开(公告)号：US4684976A

公开(公告)日：1987-08-04

申请号：US852207

申请日：1986-04-15

申请人： Shoichi Sugihara ,  Sumio Katoh

发明人： Shoichi Sugihara ,  Sumio Katoh

IPC分类号： H03H11/04 ,  H04N5/21 ,  H04N9/78 ,  H04N5/213

CPC分类号： H03H11/04 ,  H04N5/21

摘要： This invention relates to a feedback comb-type filter used for improving the S/N ratio of video signals and so constructed as to delay the output of a coefficient multiplier and to get a feedback delay signal contrary to the conventional one which gives to the coefficient multiplier the filter output, that is, the signal to be output to the exterior, thereby enabling to improve the S/N ratio only by varying the coefficient of the coefficient multiplier, also constructed to be able to cut off the feedback delay signal to suppress generation of pseudo signal and use one low pass filter for both the delay circuit and the limit of horizontal frequency band to reduce the components in number, thereby expecting improvements in accuracy and reliability.

摘要翻译： 本发明涉及一种用于提高视频信号的S / N比的反馈梳状滤波器，并被构造成延迟系数乘法器的输出并获得反馈延迟信号，这与传统系数的系数相反 对滤波器输出进行乘法器，即输出到外部的信号，从而能够仅通过改变系数乘法器的系数来提高S / N比，也可构成为能够截止反馈延迟信号以抑制 产生伪信号，并对延迟电路和水平频带的限制使用一个低通滤波器来减少数量的分量，从而期望提高精度和可靠性。

公开(公告)号：US09236496B2

公开(公告)日：2016-01-12

申请号：US14002794

申请日：2012-03-02

申请人： Sumio Katoh ,  Hidehito Kitakado

发明人： Sumio Katoh ,  Hidehito Kitakado

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L27/12 ,  H01L33/00 ,  H01L29/417

CPC分类号： H01L29/78693 ,  H01L27/1222 ,  H01L29/41733 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L33/0041

摘要： The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.

摘要翻译： 本发明提供一种薄膜晶体管及其制造方法，该薄膜晶体管能够减小沟道层的沟道宽度方向的端部流过的截止电流。

公开(公告)号：US09123820B2

公开(公告)日：2015-09-01

申请号：US13640354

申请日：2011-03-02

申请人： Sumio Katoh

发明人： Sumio Katoh

IPC分类号： H01L29/04 ,  H01L29/786 ,  H01L29/417 ,  G02F1/1368 ,  H01L29/66

CPC分类号： H01L29/7869 ,  G02F1/1368 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device (ST) includes a substrate (11), a gate electrode (12b), a gate insulating film (13b), an oxide semiconductor film (14b) including a channel part (14bc) formed in a position facing the gate electrode (12b), a source electrode (15bs), and a drain electrode (15bd). The source electrode (15bs) and the drain electrode (15bd) is arranged so as not to overlap with the gate electrode (12b) as viewed in the plane. A region adjacent to the gate electrode (12b) and the source electrode (15bs) and a region adjacent to the gate electrode (12b) and the drain electrode (15bd) are, in a region where the source electrode (15bs) and the drain electrode (15bd) does not overlap with the gate electrode (12b), processed such that resistance in a region of the oxide semiconductor film (14b) including a surface thereof is reduced.

摘要翻译： 半导体器件（ST）包括衬底（11），栅极电极（12b），栅极绝缘膜（13b），氧化物半导体膜（14b），其包括形成在面对栅电极的位置的沟道部分 （12b），源极（15bs）和漏极（15bd）。 源极电极（15bs）和漏极电极（15bd）被布置成与平面中的栅电极（12b）不重叠。 与栅电极（12b）和源电极（15bs）相邻的区域和与栅电极（12b）和漏电极（15bd）相邻的区域在源电极（15bs）和漏极 电极（15bd）不与栅电极（12b）重叠，进行处理，使得包括其表面的氧化物半导体膜（14b）的区域中的电阻降低。