公开(公告)号：US07274690B1

公开(公告)日：2007-09-25

申请号：US10302436

申请日：2002-11-22

申请人： Sung Soo Park ,  Sung Man Park ,  Jung Wook Cho ,  Edward Pak

发明人： Sung Soo Park ,  Sung Man Park ,  Jung Wook Cho ,  Edward Pak

IPC分类号： H04L12/50 ,  H04L12/56 ,  H04Q11/00 ,  G06F13/00

CPC分类号： H04L49/101 ,  H04L12/4625

摘要： A content addressable merged queue (camQ) architecture for high-speed switch fabrics reduces the memory requirement for crossbar switch input and output queues using memory cells and age tag comparators. CamQ emulates VOQ FIFO for each supporting priority, eliminating HOL blocking. Multiple QoS levels are supported cost effectively at higher traffic bandwidth limits. Content addressable memory (CAM) cells store payload destinations, which can be addressed by cell priorities. Once a priority for QoS is decided, all the cells with the selected priority in the payload can make connection requests to destination ports directly through the CAM structure. An age tag is assigned to incoming cells and fast age tag comparators provide FCFS features by selecting the oldest cell. Small memory sizes prevent the bottlenecking in ingress and egress queues. A CIOQ crossbar has a fast switching speed, emulating a FIFO output queue switch. Age and priority are interleaved to schedule switching.

摘要翻译： 用于高速交换结构的内容可寻址合并队列（camQ）架构减少了使用存储器单元和年龄标签比较器的交叉开关输入和输出队列的存储器需求。 CamQ模拟每个支持优先级的VOQ FIFO，从而消除了HOL阻塞。 在更高的流量带宽限制下，可以以成本有效的方式支持多个QoS级别。 内容可寻址存储器（CAM）单元存储有效载荷目的地，其可以通过小区优先级来寻址。 一旦确定了QoS的优先级，则有效载荷中具有选定优先级的所有小区可以直接通过CAM结构向目的端口发送连接请求。 年龄标签被分配给传入的单元格，快速年龄标签比较器通过选择最旧的单元格来提供FCFS功能。 小内存大小可防止入口和出口队列中的瓶颈。 CIOQ交叉开关具有快速切换速度，仿真FIFO输出队列开关。 年龄和优先级被交织以调度切换。

公开(公告)号：US5945861A

公开(公告)日：1999-08-31

申请号：US873860

申请日：1997-06-12

申请人： Jae Goo Lee ,  Sung Man Park

发明人： Jae Goo Lee ,  Sung Man Park

IPC分类号： G06F1/10 ,  G11C7/22 ,  G11C11/407 ,  H03K5/13 ,  H03K5/135 ,  H03K5/14

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135

摘要： The circuit of the present invention prevents a multi-locking phenomenon, reduces power consumption and provides an accurately locked internal clock signal. A delay unit sequentially delays an external clock signal through a plurality of unit delay terminals. A sampling and computation unit maintains the levels of signals from the unit delay terminals connected after a predetermined unit delay terminal, in which a locking phenomenon occurs, to a predetermined level when a delay clock signal among a plurality of delay clock signals from the unit delay terminals is locked. An output unit outputs a delay clock signal locked to an external clock signal in accordance with an output from the sampling and computation unit.

摘要翻译： 本发明的电路防止多锁现象，降低功耗并提供精确锁定的内部时钟信号。 延迟单元通过多个单元延迟端子顺序地延迟外部时钟信号。 采样和计算单元在来自单位延迟的多个延迟时钟信号中的延迟时钟信号之后，将来自发生锁定现象的预定单元延迟端子之后连接的单元延迟端子的信号电平维持在预定电平 终端被锁定。 输出单元根据采样和计算单元的输出输出锁定到外部时钟信号的延迟时钟信号。

公开(公告)号：US20150163656A1

公开(公告)日：2015-06-11

申请号：US14009227

申请日：2011-10-19

申请人： Hee-Jong Son ,  Han-Koon Nam ,  Sung-Man Park ,  Jae-Woo Park ,  Hyuk-Soo Jin

发明人： Hee-Jong Son ,  Han-Koon Nam ,  Sung-Man Park ,  Jae-Woo Park ,  Hyuk-Soo Jin

IPC分类号： H04W8/02

CPC分类号： H04L61/2521 ,  H04L61/2015 ,  H04L61/6022 ,  H04W8/26 ,  H04W84/12

摘要： A wireless local area network (WLAN) system is disclosed. The WLAN system includes a first access point (AP), and a second AP which has a same service set identifier (SSID) as that of the first AP, wherein the first AP and the second AP are configured to respectively perform a network address translation (NAT) and have a same virtual media access control (MAC) address. The WLAN system according to the present disclosure supports successful roaming between APs which belong to different networks regardless of the type of the wireless terminal.

摘要翻译： 公开了一种无线局域网（WLAN）系统。 WLAN系统包括第一接入点（AP）和具有与第一AP相同的服务集标识符（SSID）的第二AP，其中，第一AP和第二AP被配置为分别执行网络地址转换 （NAT）并具有相同的虚拟媒体访问控制（MAC）地址。 根据本公开的WLAN系统支持属于不同网络的AP之间的成功漫游，而不管无线终端的类型如何。

公开(公告)号：US20080025115A1

公开(公告)日：2008-01-31

申请号：US11781380

申请日：2007-07-23

申请人： Jun-bae KIM ,  Jin-ho RYU ,  Sung-man PARK

发明人： Jun-bae KIM ,  Jin-ho RYU ,  Sung-man PARK

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/14 ,  G11C5/04 ,  G11C29/12015

摘要： Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data strobe signal may be delayed to synchronize with test data. Because a test device need not supply the data strobe signal, the number of semiconductor memory modules that can be simultaneously tested can be increased, and an average test time for a unit memory module can be decreased.

摘要翻译： 提供了一种使用半导体存储器件的内部时钟信号作为数据选通信号来测试半导体存储器件的方法和系统。 内部产生的数据选通信号可能被延迟以与测试数据同步。 由于测试装置不需要提供数据选通信号，所以能够同时测试的半导体存储器模块的数量可以增加，并且可以减少单位存储器模块的平均测试时间。

公开(公告)号：US07352764B1

公开(公告)日：2008-04-01

申请号：US10762950

申请日：2004-01-21

申请人： Sung Soo Park ,  Sung Man Park ,  Jung Wook Cho

发明人： Sung Soo Park ,  Sung Man Park ,  Jung Wook Cho

IPC分类号： H04L12/28

CPC分类号： H04L12/5601 ,  H04L49/1576 ,  H04L49/3009 ,  H04L49/309 ,  H04L2012/5629 ,  H04L2012/5651 ,  H04L2012/5665 ,  H04L2012/5681

摘要： A content addressable merged queue (camQ) architecture for switching data. The camQ architecture comprises a first array of priority cells for indicating a priority of a plurality of cells and a second array of destination cells for indicating a destination of the plurality of cells. A priority selector is operable to select a portion of said plurality of cells according to a priority selection. A grant generator is operable to grant at least one connection request associated with cells of the portion.

摘要翻译： 用于切换数据的内容可寻址合并队列（camQ）架构。 camQ架构包括用于指示多个小区的优先级的第一优先级小区阵列和用于指示多个小区的目的地的目的地小区的第二阵列。 优先级选择器可操作以根据优先级选择来选择所述多个小区的一部分。 授权生成器可操作地授予与该部分的单元相关联的至少一个连接请求。

公开(公告)号：US20070216456A1

公开(公告)日：2007-09-20

申请号：US11651487

申请日：2007-01-10

申请人： Jeong-Hoon Kook ,  Sung-Man Park

发明人： Jeong-Hoon Kook ,  Sung-Man Park

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0818

摘要： A delay locked loop includes a variable delay unit, a phase inversion unit, a delay selecting unit, a delay control unit and an inversion control unit. The variable delay unit delays a reference clock signal based on phase difference between a first feedback clock signal and a reference clock signal, outputted from the delay control unit. The phase inversion unit selectively inverts the delayed clock signal in response to a phase inversion control signal and generates a reproduction clock signal. The delay selecting unit selectively delays the first feedback clock signal corresponding to the reproduction clock signal in response to an inversion control termination signal to generate a second feedback clock signal. The inversion control unit generates the phase inversion control signal when the phase difference between the delayed feedback clock signal and the reference clock signal is larger than a half clock-cycle, and generates the inversion control termination signal.

摘要翻译： 延迟锁定环包括可变延迟单元，相位反转单元，延迟选择单元，延迟控制单元和反相控制单元。 可变延迟单元基于从延迟控制单元输出的第一反馈时钟信号和参考时钟信号之间的相位差来延迟参考时钟信号。 相位反转单元响应于相位反转控制信号选择性地反转延迟的时钟信号，并产生再现时钟信号。 响应于反转控制终止信号，延迟选择单元有选择地延迟对应于再现时钟信号的第一反馈时钟信号以产生第二反馈时钟信号。 当延迟反馈时钟信号和参考时钟信号之间的相位差大于半个时钟周期时，反相控制单元产生相位反转控制信号，并产生反相控制终止信号。

公开(公告)号：US5909133A

公开(公告)日：1999-06-01

申请号：US927812

申请日：1997-09-11

申请人： Sung Man Park

发明人： Sung Man Park

IPC分类号： G06F1/06 ,  G06F1/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/135 ,  H03K5/14

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135

摘要： An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock sinal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.

摘要翻译： 一种改进的时钟信号建模电路，其能够在不使用锁相环和延迟锁定环的情况下更快地在外部时钟信号中产生内部时钟信号，该延迟锁定环包括用于接收外部时钟信号并用于输出延迟时钟信号的延迟单元 ; 采样单元，用于接收延迟时钟信号并根据外部时钟信号进行采样; 比较单元，用于接收采样单元的输出，并用于顺序地比较输出; 以及输出单元，用于接收从延迟单元输出的延迟时钟信号，并根据比较单元的输出信号和外部施加的切换信号输出内部时钟信号。

公开(公告)号：US5708382A

公开(公告)日：1998-01-13

申请号：US587745

申请日：1996-01-19

申请人： Sung Man Park

发明人： Sung Man Park

IPC分类号： G06F1/06 ,  G06F1/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/135 ,  H03K5/14

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135

摘要： An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock signal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.

摘要翻译： 一种改进的时钟信号建模电路，其能够在不使用锁相环和延迟锁定环的情况下更快地在外部时钟信号中产生内部时钟信号，该延迟锁定环包括用于接收外部时钟信号并用于输出延迟时钟信号的延迟单元 ; 采样单元，用于接收延迟时钟信号并根据外部时钟信号进行采样; 比较单元，用于接收采样单元的输出，并用于顺序地比较输出; 以及输出单元，用于接收从延迟单元输出的延迟时钟信号，并根据比较单元的输出信号和外部施加的切换信号输出内部时钟信号。

公开(公告)号：US07823031B2

公开(公告)日：2010-10-26

申请号：US11781380

申请日：2007-07-23

申请人： Jun-bae Kim ,  Jin-ho Ryu ,  Sung-man Park

发明人： Jun-bae Kim ,  Jin-ho Ryu ,  Sung-man Park

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C5/04 ,  G11C29/12015

摘要： Provided are a method and system for testing a semiconductor memory device using an internal clock signal of the semiconductor memory device as a data strobe signal. The internally-generated data strobe signal may be delayed to synchronize with test data. Because a test device need not supply the data strobe signal, the number of semiconductor memory modules that can be simultaneously tested can be increased, and an average test time for a unit memory module can be decreased.

摘要翻译： 提供了使用半导体存储器件的内部时钟信号作为数据选通信号来测试半导体存储器件的方法和系统。 内部产生的数据选通信号可能被延迟以与测试数据同步。 由于测试装置不需要提供数据选通信号，所以能够同时测试的半导体存储器模块的数量可以增加，并且可以减少单位存储器模块的平均测试时间。

公开(公告)号：US20080169855A1

公开(公告)日：2008-07-17

申请号：US11809971

申请日：2007-06-04

申请人： Won-Hwa Shin ,  Sung-Man Park ,  Kwang-Il Park

发明人： Won-Hwa Shin ,  Sung-Man Park ,  Kwang-Il Park

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： An apparatus for correcting a duty cycle of an input clock signal to generate a digitally corrected clock signal includes a duty cycle detector, an analog duty cycle correcting unit, and a digital duty cycle correcting unit. The duty cycle detector generates a duty cycle signal indicating a respective duty cycle of the digitally corrected clock signal. The analog duty cycle correcting unit adjusts a current flowing through a node to adjust the respective duty cycle of the input clock signal for generating an analog corrected clock signal at the node. The digital duty cycle correcting unit adjusts the respective duty cycle of the analog corrected clock signal according to the duty cycle signal for generating the digitally corrected clock signal.

摘要翻译： 用于校正输入时钟信号的占空比以产生经数字校正的时钟信号的装置包括占空比检测器，模拟占空比校正单元和数字占空比校正单元。 占空比检测器产生指示数字校正的时钟信号的相应占空比的占空比信号。 模拟占空比校正单元调节流过节点的电流，以调整输入时钟信号的相应占空比，以在节点处产生模拟校正时钟信号。 数字占空比校正单元根据用于产生经数字校正的时钟信号的占空比信号来调整模拟校正时钟信号的相应占空比。