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公开(公告)号：US20110031584A1
公开(公告)日：2011-02-10
申请号：US12848355
申请日：2010-08-02
申请人： Syouichi KOTANI
发明人： Syouichi KOTANI
IPC分类号： H01L29/86 , H01L23/48 , H01L21/768 , H01L21/02
CPC分类号： H01L23/5227 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/94 , H01L28/10 , H01L2224/02311 , H01L2224/0233 , H01L2224/02331 , H01L2224/02377 , H01L2224/0347 , H01L2224/0384 , H01L2224/0391 , H01L2224/0401 , H01L2224/131 , H01L2224/1416 , H01L2224/94 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2224/11 , H01L2224/03 , H01L2224/13099
摘要： A first insulating film includes five extension lines formed between connection pad portions of adjacent two predetermined wiring lines. The first insulating film also includes peripheral portions of the adjacent two connection pad portions on both sides of the five extension lines. A second insulating film made of a polyimide resin or the like is formed on the upper surface of the first insulating layer by a screen printing method or ink jet method. Since a short circuit may be easily caused by electromigration in a region where the five extension lines are parallel to another, the short circuit due to the electromigration can be prevented by covering only that region with the second insulating film. Accordingly, the region where the second insulating film is formed can be as small as possible, and the semiconductor wafer does not easily warp.
摘要翻译： 第一绝缘膜包括在相邻的两个预定布线的连接焊盘部分之间形成的五个延伸线。 第一绝缘膜还包括在五个延长线的两侧上的相邻两个连接焊盘部分的周边部分。 通过丝网印刷法或喷墨法在第一绝缘层的上表面上形成由聚酰亚胺树脂等制成的第二绝缘膜。 由于在五个延长线平行于另一个的区域中电迁移可能容易引起短路，所以可以通过仅用第二绝缘膜覆盖该区域来防止由电迁移引起的短路。 因此，形成第二绝缘膜的区域尽可能地小，并且半导体晶片不容易翘曲。
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2.发明授权Semiconductor device having alignment post electrode and method of manufacturing the same 有权具有对位柱电极的半导体器件及其制造方法公开(公告)号：US07944064B2
公开(公告)日：2011-05-17
申请号：US11656866
申请日：2007-01-22
申请人： Shinji Wakisaka , Tomohiro Ito , Shigeru Yokoyama , Osamu Kuwabara , Norihiko Kaneko , Syouichi Kotani
发明人： Shinji Wakisaka , Tomohiro Ito , Shigeru Yokoyama , Osamu Kuwabara , Norihiko Kaneko , Syouichi Kotani
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L23/3114 , H01L24/11 , H01L24/13 , H01L2223/54453 , H01L2223/54466 , H01L2223/5448 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05647 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
摘要翻译： 半导体器件包括具有多个半导体器件形成区域和具有与半导体器件形成区域相同的平面尺寸的对准标记形成区域的半导体衬底，形成在每个半导体器件形成区域中的多个柱状电极， 以及形成在对准标记形成区域中并且数量小于形成在每个半导体器件形成区域中的柱状电极的定向柱状电极。
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公开(公告)号：US08421187B2
公开(公告)日：2013-04-16
申请号：US12848355
申请日：2010-08-02
申请人： Syouichi Kotani
发明人： Syouichi Kotani
CPC分类号： H01L23/5227 , H01L23/3114 , H01L23/3192 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/94 , H01L28/10 , H01L2224/02311 , H01L2224/0233 , H01L2224/02331 , H01L2224/02377 , H01L2224/0347 , H01L2224/0384 , H01L2224/0391 , H01L2224/0401 , H01L2224/131 , H01L2224/1416 , H01L2224/94 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2224/11 , H01L2224/03 , H01L2224/13099
摘要： A first insulating film includes five extension lines formed between connection pad portions of adjacent two predetermined wiring lines. The first insulating film also includes peripheral portions of the adjacent two connection pad portions on both sides of the five extension lines. A second insulating film made of a polyimide resin or the like is formed on the upper surface of the first insulating layer by a screen printing method or ink jet method. Since a short circuit may be easily caused by electromigration in a region where the five extension lines are parallel to another, the short circuit due to the electromigration can be prevented by covering only that region with the second insulating film. Accordingly, the region where the second insulating film is formed can be as small as possible, and the semiconductor wafer does not easily warp.
摘要翻译： 第一绝缘膜包括在相邻的两个预定布线的连接焊盘部分之间形成的五个延伸线。 第一绝缘膜还包括在五个延长线的两侧上的相邻两个连接焊盘部分的周边部分。 通过丝网印刷法或喷墨法在第一绝缘层的上表面上形成由聚酰亚胺树脂等制成的第二绝缘膜。 由于在五个延长线平行于另一个的区域中电迁移可能容易引起短路，所以可以通过仅用第二绝缘膜覆盖该区域来防止由电迁移引起的短路。 因此，形成第二绝缘膜的区域尽可能地小，并且半导体晶片不容易翘曲。
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4.发明申请Semiconductor device having alignment post electrode and method of manufacturing the same 有权具有对位柱电极的半导体器件及其制造方法公开(公告)号：US20070164432A1
公开(公告)日：2007-07-19
申请号：US11656866
申请日：2007-01-22
申请人： Shinji Wakisaka , Tomohiro Ito , Shigeru Yokoyama , Osamu Kuwabara , Norihiko Kaneko , Syouichi Kotani
发明人： Shinji Wakisaka , Tomohiro Ito , Shigeru Yokoyama , Osamu Kuwabara , Norihiko Kaneko , Syouichi Kotani
CPC分类号： H01L23/544 , H01L23/3114 , H01L24/11 , H01L24/13 , H01L2223/54453 , H01L2223/54466 , H01L2223/5448 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05647 , H01L2224/11 , H01L2224/1147 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor substrate which has a plurality of semiconductor device formation regions and alignment mark formation region having the same planar size as that of the semiconductor device formation region, a plurality of post electrodes which are formed in each semiconductor device formation region, and an alignment post electrode which is formed in the alignment mark formation region and smaller in number than the post electrodes formed in each semiconductor device formation region.
摘要翻译： 半导体器件包括具有多个半导体器件形成区域和具有与半导体器件形成区域相同的平面尺寸的对准标记形成区域的半导体衬底，形成在每个半导体器件形成区域中的多个柱状电极， 以及形成在对准标记形成区域中并且数量小于形成在每个半导体器件形成区域中的柱状电极的定向柱状电极。
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