公开(公告)号：US20070117297A1

公开(公告)日：2007-05-24

申请号：US11656717

申请日：2007-01-23

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L21/8234

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

公开(公告)号：US06917085B2

公开(公告)日：2005-07-12

申请号：US10728811

申请日：2003-12-08

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66598 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

摘要翻译： 本发明提供一种使用L形间隔物的半导体晶体管。 半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。 在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。 高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。 中等浓度接合区域位于高浓度和低浓度接合区域之间。

公开(公告)号：US06524902B2

公开(公告)日：2003-02-25

申请号：US10001619

申请日：2001-10-23

申请人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

发明人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

IPC分类号： H01L218238

CPC分类号： H01L21/2807 ,  H01L21/823842

摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.

摘要翻译： 在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个 一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同 与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。 与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。 例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分Ge浓度低于10 ％。

公开(公告)号：US07195987B2

公开(公告)日：2007-03-27

申请号：US11141275

申请日：2005-05-31

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L21/76

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si 1-x Ge Ge层还设置在电绝缘层和未应变硅有源层之间。 Si 1-x N Ge x S层与未应变的硅有源层形成第一结，并且其中的Ge的分级浓度在从第一方向延伸的第一方向上单调减小 峰值电平朝向未应变硅活性层的表面。 峰值Ge浓度水平大于x = 0.15，并且Si 1-x Ga x层中的Ge浓度从峰值水平变化到小于约 x = 0.1。 Ge在第一结处的浓度可能是突然的。 更优选的是，Si 1-x Ge 2 x层中的Ge的浓度从0.2

公开(公告)号：US06881630B2

公开(公告)日：2005-04-19

申请号：US10426509

申请日：2003-04-30

申请人： Won-sang Song ,  Jung-woo Park ,  Gil-gwang Lee ,  Tae-hee Choe

发明人： Won-sang Song ,  Jung-woo Park ,  Gil-gwang Lee ,  Tae-hee Choe

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

摘要： Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure. These methods may comprise the steps of: providing a integrated circuit substrate having surface and a gate on the integrated circuit substrate; subsequently removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.

摘要翻译： 场效应晶体管（FET）包括具有表面的集成电路基板和表面上的栅极。 衬底中的一对凹陷区域位于表面下方。 凹陷区域中的各个位于门的相应的相对侧上。 凹陷区域中的每一个限定了侧壁和底板。 每个凹陷区域上的升高的源极/漏极结构至少与栅极相邻的栅极远离栅极一样厚。 栅极间隔物可以包括在栅极和升高的源极/漏极区域之间。 栅极隔离物可以包括绝缘膜。 优选地，源极/漏极结构延伸到凹陷区域的侧壁。 升高的源极/漏极结构优选没有邻近栅极的刻面。 本发明还涉及用于制造具有升高的源极/漏极结构的场效应晶体管（FET）的方法。 这些方法可以包括以下步骤：在集成电路基板上提供具有表面和栅极的集成电路基板; 随后去除所述集成电路基板的部分，以在所述集成电路基板的表面下方形成一对凹陷区域，所述凹陷区域由所述集成电路基板中的底板和侧壁限定; 并且在每个凹陷区域的地板和侧壁上外延生长一层。

公开(公告)号：US06794306B2

公开(公告)日：2004-09-21

申请号：US10463554

申请日：2003-06-17

申请人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

发明人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

IPC分类号： H01L2100

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S438/933

摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

摘要翻译： 公开了具有栅极全部（GAA）型晶体管的半导体器件及其制造方法。 制备由SOI层，掩埋氧化物层和下基板构成的SOI衬底。 SOI层具有硅锗层和硅层的至少一个单元双层。 图案化SOI层，以形成一定方向的有源层图案。 形成绝缘层以覆盖有源层图案。 在覆盖有绝缘层的有源层图案上堆叠蚀刻停止层。 蚀刻停止层被图案化并在沟道区域与有源层图案交叉的栅极区域去除。 绝缘层在栅极区域被去除。 硅锗层被各向同性地蚀刻并选择性地去除以在有源层图案的沟道区域形成空腔。 在选择性地去除硅锗层的状态下，形成栅极绝缘层以覆盖有源层图案的暴露表面。 通过化学气相沉积（CVD）将栅极导电层层叠在基板上，以填充包括空腔的栅极区域。 有源层图案的沟道区域的中间部分可以被图案化以被划分成一行形成的多个图案。

公开(公告)号：US06693013B2

公开(公告)日：2004-02-17

申请号：US10103759

申请日：2002-03-25

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas. A method of fabricating the semiconductor transistor includes a process, where the high- and medium-concentration junction areas are formed simultaneously by the same ion-implantation step and the substrate is annealed before forming the low-concentration junction area.

摘要翻译： 本发明提供一种使用L形间隔物的半导体晶体管及其制造方法。 半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。 在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。 高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。 中等浓度接合区域位于高浓度和低浓度接合区域之间。 制造半导体晶体管的方法包括一个过程，其中通过相同的离子注入步骤同时形成高浓度和中等浓度的结区，并且在形成低浓度结区之前将衬底退火。

公开(公告)号：US06633066B1

公开(公告)日：2003-10-14

申请号：US09711706

申请日：2000-11-13

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L310392

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1−xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1−xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1−xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1−xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 还可以在电绝缘层和未应变硅活性层之间设置Si 1-x Ge x 层。 Si 1-x Ge x 层与未应变硅活性层形成第一结，并具有梯度浓度 Ge在从峰值电平向未应变硅有源层的表面延伸的第一方向上单调减小。 Peal Ge浓度水平大于x = 0.15，并且Si 1-x Ge x 层在峰值电平变化到在第一结处小于约x = 0.1的电平。 Ge在第一结处的浓度可能是突然的。 更优选的是，Si >

层中的Ge的浓度， x <0.4到第一结处x = 0的水平。 相对于表面，Si 1-x Ge x 层也具有退化的砷掺杂特性。 >

公开(公告)号：US06605847B2

公开(公告)日：2003-08-12

申请号：US10039151

申请日：2002-01-03

申请人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

发明人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

IPC分类号： H01L29786

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S438/933

摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

公开(公告)号：US07642140B2

公开(公告)日：2010-01-05

申请号：US11656717

申请日：2007-01-23

申请人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

发明人： Geum-jong Bae ,  Tae-hee Choe ,  Sang-su Kim ,  Hwa-sung Rhee ,  Nae-in Lee ,  Kyung-wook Lee

IPC分类号： H01L21/84

CPC分类号： H01L29/66916 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78687 ,  H01L29/802

摘要： CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1-xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1-xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1-xGex layer varies from the peak level where 0.2

摘要翻译： CMOS集成电路器件包括电绝缘层和电绝缘层上的非限制性硅有源层。 绝缘栅电极也设置在未应变硅有源层的表面上。 Si1-xGex层也设置在电绝缘层和未应变硅有源层之间。 Si1-xGex层与未应变的硅有源层形成第一结，并且其中Ge的分级浓度在从峰值电平朝向未应变硅有源层的表面延伸的第一方向上单调减小。 峰值Ge浓度水平大于x = 0.15，并且Si1-xGex层中的Ge浓度在第一结处从峰值水平变化到小于约x = 0.1的水平。 Ge在第一结处的浓度可能是突然的。 更优选地，Si1-xGex层中的Ge的浓度从0.2