公开(公告)号：US06917085B2

公开(公告)日：2005-07-12

申请号：US10728811

申请日：2003-12-08

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66598 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

摘要翻译： 本发明提供一种使用L形间隔物的半导体晶体管。 半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。 在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。 高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。 中等浓度接合区域位于高浓度和低浓度接合区域之间。

公开(公告)号：US06693013B2

公开(公告)日：2004-02-17

申请号：US10103759

申请日：2002-03-25

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas. A method of fabricating the semiconductor transistor includes a process, where the high- and medium-concentration junction areas are formed simultaneously by the same ion-implantation step and the substrate is annealed before forming the low-concentration junction area.

摘要翻译： 本发明提供一种使用L形间隔物的半导体晶体管及其制造方法。 半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。 在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。 高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。 中等浓度接合区域位于高浓度和低浓度接合区域之间。 制造半导体晶体管的方法包括一个过程，其中通过相同的离子注入步骤同时形成高浓度和中等浓度的结区，并且在形成低浓度结区之前将衬底退火。

公开(公告)号：US06750532B2

公开(公告)日：2004-06-15

申请号：US10336604

申请日：2003-01-03

申请人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

发明人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

IPC分类号： H01L29167

CPC分类号： H01L21/2807 ,  H01L21/823842

摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.

摘要翻译： 在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个 一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同 与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。 与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。 例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分中的Ge浓度低于10 ％。

公开(公告)号：US06524902B2

公开(公告)日：2003-02-25

申请号：US10001619

申请日：2001-10-23

申请人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

发明人： Hwa-Sung Rhee ,  Geum-Jong Bae ,  Tae-Hee Choe ,  Sang-Su Kim ,  Nae-In Lee

IPC分类号： H01L218238

CPC分类号： H01L21/2807 ,  H01L21/823842

摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.

摘要翻译： 在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个 一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同 与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。 与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。 例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分Ge浓度低于10 ％。

公开(公告)号：US06881621B2

公开(公告)日：2005-04-19

申请号：US10713216

申请日：2003-11-17

申请人： Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

发明人： Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

IPC分类号： H01L27/04 ,  H01L21/00 ,  H01L21/02 ,  H01L21/68 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/62 ,  H01L27/01 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/00 ,  H01L29/72 ,  H01L31/0392

CPC分类号： H01L21/6835 ,  H01L21/743 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68363 ,  H01L2924/30105

摘要： A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch stopping layer, which may be a silicon nitride layer, on a front surface of a supporting substrate; contacting the etch stopping layer with the buried oxide layer to bond the semiconductor substrate to the supporting substrate; and selectively removing the semiconductor substrate and the first semiconductor layer to expose the second semiconductor layer. The method may additionally include forming a buffer oxide layer between the supporting substrate and the etch stopping layer.

摘要翻译： 制造SOI衬底的方法包括在半导体衬底的前表面上顺序地形成可以是多孔半导体层或气泡层的第一半导体层，第二半导体层和掩埋氧化物层，形成蚀刻停止 层，其可以是氮化硅层;在支撑衬底的前表面上; 使所述蚀刻停止层与所述掩埋氧化物层接触以将所述半导体衬底接合到所述支撑衬底; 以及选择性地去除所述半导体衬底和所述第一半导体层以暴露所述第二半导体层。 该方法还可以包括在支撑衬底和蚀刻停止层之间形成缓冲氧化物层。

公开(公告)号：US06670677B2

公开(公告)日：2003-12-30

申请号：US09989112

申请日：2001-11-21

申请人： Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

发明人： Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

IPC分类号： H01L2972

CPC分类号： H01L21/6835 ,  H01L21/743 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68363 ,  H01L2924/30105

摘要： A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.

摘要翻译： 提供了具有蚀刻停止层的SOI衬底，在SOI衬底上制造的SOI集成电路，以及制造两者的方法。 SOI衬底包括支撑衬底，沉积在支撑衬底上的蚀刻停止层，依次层叠在蚀刻停止层上的掩埋氧化物层和半导体层。 蚀刻停止层优选地相对于掩埋氧化物层具有蚀刻选择性。 优选形成器件隔离层以限定有源区。 选择性地去除器件隔离，掩埋氧化物和蚀刻停止层，以形成暴露支撑衬底的第一和第二孔而不损坏支撑衬底。 因此，在暴露的支撑衬底上生长的半导体外延层具有没有结晶缺陷的单晶结构。 因此，当在外延层的表面形成杂质区时，可以形成具有优异的漏电流特性的高性能PN二极管。

公开(公告)号：US06794306B2

公开(公告)日：2004-09-21

申请号：US10463554

申请日：2003-06-17

申请人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

发明人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

IPC分类号： H01L2100

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S438/933

摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

摘要翻译： 公开了具有栅极全部（GAA）型晶体管的半导体器件及其制造方法。 制备由SOI层，掩埋氧化物层和下基板构成的SOI衬底。 SOI层具有硅锗层和硅层的至少一个单元双层。 图案化SOI层，以形成一定方向的有源层图案。 形成绝缘层以覆盖有源层图案。 在覆盖有绝缘层的有源层图案上堆叠蚀刻停止层。 蚀刻停止层被图案化并在沟道区域与有源层图案交叉的栅极区域去除。 绝缘层在栅极区域被去除。 硅锗层被各向同性地蚀刻并选择性地去除以在有源层图案的沟道区域形成空腔。 在选择性地去除硅锗层的状态下，形成栅极绝缘层以覆盖有源层图案的暴露表面。 通过化学气相沉积（CVD）将栅极导电层层叠在基板上，以填充包括空腔的栅极区域。 有源层图案的沟道区域的中间部分可以被图案化以被划分成一行形成的多个图案。

公开(公告)号：US06605847B2

公开(公告)日：2003-08-12

申请号：US10039151

申请日：2002-01-03

申请人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

发明人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

IPC分类号： H01L29786

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S438/933

摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

公开(公告)号：US06518645B2

公开(公告)日：2003-02-11

申请号：US10095169

申请日：2002-03-11

申请人： Geum-Jong Bae ,  Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee

发明人： Geum-Jong Bae ,  Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee

IPC分类号： H01L31117

CPC分类号： H01L29/66772 ,  H01L29/78615 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an SOI-type semiconductor device and a method of forming the same a semiconductor device is formed in an SOI-type substrate that is composed of a lower silicon layer, a buried oxide layer, and an SOI layer. The SOI substrate includes a device region isolated by a device isolation layer and the buried oxide layer, in which a source/drain region for forming at least one MOSFET at a body composed of the SOI layer is formed; and a ground region which is isolated from the device region by the device isolation layer and is composed of the body. A bottom portion of the device isolation layer is separated from the buried oxide layer by a connecting portion that electrically connects a body of the device region to a body of the ground region through the SOI layer. A silicon germanium layer is formed in the SOI layer, and at least partially remains at the SOI layer connecting the body of the device region to the body of the ground region in the connecting portion. Preferably, the device isolation layer is a trench-type isolation layer. The silicon germanium layer is formed at an interface between the SOI layer and the lowest portion of the SOI layer, i.e., a buried oxide layer, or is sandwiched between silicon layers that constitute the SOI layer under the SOI layer.