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公开(公告)号：US06864532B2
公开(公告)日：2005-03-08
申请号：US10175294
申请日：2002-06-20
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译： 沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。 栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。 第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。 第二部分仅包括氧化膜并且比第一部分厚。 因此，可以减小沟槽的上下角部的电场集中以提高耐压。 此外，沟槽的端部可以具有比第一部分更厚的绝缘层。
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公开(公告)号：US08056707B2
公开(公告)日：2011-11-15
申请号：US10590147
申请日：2005-05-16
CPC分类号： B32B15/14 , B32B5/28 , B32B7/12 , B32B2305/182 , B32B2311/12 , B32B2311/18 , B32B2311/24 , B32B2311/30 , B32B2327/18 , B65G15/38
摘要： Provided are a heat resistant laminated conveyor belt and manufacturing method thereof by which a belt surface pressure when a liner and corrugated core paper are pressed and bonded together can be increased to thereby enhance a bonding performance. The heat resistant laminated conveyor belt comprises a belt core layer 11 made by a heat resistant non-metallic fiber substrate being impregnated with a fluororesin dispersion and then dried and sintered and a surface layer 13 (plain weave wire, etc., for example) formed on the belt core layer 11 via an adhesive layer 12 made by a fluororesin film, the surface layer having a fabric structure using an element wire or wires made of a ferrous metal or having a structure in which the element wire or wires are arranged together.As the surface layer 13, a fabric structure using an element wire or wires made of a non-ferrous metal, inorganic compound, organic compound or carbon is used or a structure in which the element wire or wires are arranged together (plain weave wire, parallel wire, etc., for example) is used. As the element wires, stranded wires, parallel wires or the like are used.
摘要翻译： 提供一种耐热层压输送带及其制造方法，通过该方法可以增加衬垫和波纹芯纸被压接在一起的带表面压力，从而提高接合性能。 耐热层叠传送带包括由耐热非金属纤维基材制成的带芯层11，浸渍有氟树脂分散体，然后干燥并烧结，形成表面层13（例如平纹丝等） 通过由氟树脂膜制成的粘合剂层12在带芯层11上，表面层具有使用元素丝的织物结构或由黑色金属制成的线或具有将元件线或线布置在一起的结构。 作为表面层13，使用使用由有色金属，无机化合物，有机化合物或碳制成的元素线或线的织物结构或将元件线或线布置在一起的结构（平纹丝， 使用平行线等）。 作为元件线，使用绞线，平行线等。
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公开(公告)号：US20090014122A1
公开(公告)日：2009-01-15
申请号：US10590147
申请日：2005-05-16
IPC分类号： B65G17/00
CPC分类号： B32B15/14 , B32B5/28 , B32B7/12 , B32B2305/182 , B32B2311/12 , B32B2311/18 , B32B2311/24 , B32B2311/30 , B32B2327/18 , B65G15/38
摘要： Provided are a heat resistant laminated conveyor belt and manufacturing method thereof by which a belt surface pressure when a liner and corrugated core paper are pressed and bonded together can be increased to thereby enhance a bonding performance. The heat resistant laminated conveyor belt comprises a belt core layer 11 made by a heat resistant non-metallic fiber substrate being impregnated with a fluororesin dispersion and then dried and sintered and a surface layer 13 (plain weave wire, etc., for example) formed on the belt core layer 11 via an adhesive layer 12 made by a fluororesin film, the surface layer having a fabric structure using an element wire or wires made of a ferrous metal or having a structure in which the element wire or wires are arranged together.As the surface layer 13, a fabric structure using an element wire or wires made of a non-ferrous metal, inorganic compound, organic compound or carbon is used or a structure in which the element wire or wires are arranged together (plain weave wire, parallel wire, etc., for example) is used. As the element wires, stranded wires, parallel wires or the like are used.
摘要翻译： 提供一种耐热层压输送带及其制造方法，通过该方法可以增加衬垫和波纹芯纸被压接在一起的带表面压力，从而提高接合性能。 耐热层叠传送带包括由耐热非金属纤维基材制成的带芯层11，浸渍有氟树脂分散体，然后干燥并烧结，形成表面层13（例如平纹丝等） 通过由氟树脂膜制成的粘合剂层12在带芯层11上，表面层具有使用元素丝的织物结构或由黑色金属制成的线或具有将元件线或线布置在一起的结构。 作为表面层13，使用使用由有色金属，无机化合物，有机化合物或碳制成的元素线或线的织物结构或将元件线或线布置在一起的结构（平纹丝， 使用平行线等）。 作为元件线，使用绞线，平行线等。
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公开(公告)号：US20050090060A1
公开(公告)日：2005-04-28
申请号：US10974838
申请日：2004-10-28
申请人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
发明人： Takaaki Aoki , Yutaka Tomatsu , Akira Kuroyanagi , Mikimasa Suzuki , Hajime Soga , Takafumi Arakawa , Yukio Tsuzuki
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/7397
摘要： A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.
摘要翻译： 沟槽栅型晶体管具有形成在沟槽的内壁上的栅极绝缘膜。 栅极绝缘膜包括位于沟槽的壁上的第一部分和位于沟槽的上部和底部的第二部分。 第一部分包括第一氧化膜，氮化物膜和第二氧化物膜。 第二部分仅包括氧化膜并且比第一部分厚。 因此，可以减小沟槽的上下角部的电场集中以提高耐压。 此外，沟槽的端部可以具有比第一部分更厚的绝缘层。
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5.发明授权Method for manufacturing semiconductor device having trench filled with polysilicon 失效制造具有填充有多晶硅的沟槽的半导体器件的方法公开(公告)号：US06624044B2
公开(公告)日：2003-09-23
申请号：US09852690
申请日：2001-05-11
申请人： Hiroyasu Ito , Takafumi Arakawa , Masatoshi Kato
发明人： Hiroyasu Ito , Takafumi Arakawa , Masatoshi Kato
IPC分类号： H01L2176
CPC分类号： H01L29/66181 , H01L21/31055 , H01L21/763 , H01L27/10861
摘要： First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film. Then, the selective thin film is etched (etched back) so that a part of the selective thin film remains in a depression of the polysilicon film, as a self-aligning mask. The polysilicon film is further etched with the self-aligning mask, thereby forming a polysilicon embedded layer in the trench with a flat surface.
摘要翻译： 首先，半导体衬底的沟槽填充有沉积在半导体衬底的表面上的多晶硅膜。 在多晶硅膜上形成具有相对于多晶硅膜的蚀刻选择性的选择性薄膜。 然后，作为自对准掩模，选择性薄膜被蚀刻（回蚀刻），使得一部分选择性薄膜保持在多晶硅膜的凹陷中。 用自对准掩模进一步蚀刻多晶硅膜，从而在沟槽中形成具有平坦表面的多晶硅嵌入层。
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公开(公告)号：US07037788B2
公开(公告)日：2006-05-02
申请号：US10786107
申请日：2004-02-26
申请人： Hiroyasu Ito , Masatoshi Kato , Takafumi Arakawa
发明人： Hiroyasu Ito , Masatoshi Kato , Takafumi Arakawa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/7811
摘要： By improving profile of impurity concentration in a channel portion of an FET or an IGBT of a trench gate type, variation of threshold value is lessened, and a destruction caused by current concentration is prevented while suppressing deterioration of cut-off characteristics. An island of a base region of p-type is formed in a semiconductor substrate of n-type by carrying out high acceleration ion implantation twice followed by annealing, so that the impurity concentration profile in a channel portion changes gradually in a depth direction. Accordingly, it is possible to lessen variation of the threshold value and to reduce pinch resistance while at the same time improving sub-threshold voltage coefficient and conductance characteristics.
摘要翻译： 通过改善FET或沟槽栅极型IGBT的沟道部分中的杂质浓度分布，可以减小阈值的变化，同时抑制截止特性劣化的电流集中的破坏。 通过进行高加速度离子注入两次然后退火，在n型半导体衬底中形成p型基区的岛，使得沟道部分中的杂质浓度分布在深度方向上逐渐变化。 因此，可以减小阈值的变化并减小钳位电阻，同时提高次阈值电压系数和电导特性。
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公开(公告)号：US06448139B2
公开(公告)日：2002-09-10
申请号：US09875026
申请日：2001-06-07
申请人： Hiroyasu Ito , Takafumi Arakawa , Masatoshi Kato
发明人： Hiroyasu Ito , Takafumi Arakawa , Masatoshi Kato
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/66348 , H01L29/945
摘要： A semiconductor substrate has a trench for forming a gate insulation film and a gate electrode therein, or an insulated isolation isolating a semiconductor element like a transistor from other elements. The trench is formed by anisotropic dry etching. After that, a shape of the trench is improved so that a bottom portion and an opening portion are rounded or tapered by a wet process using a mixed solution containing hydrofluoric acid and nitric acid. By modifying the shape of the trench, electrical characteristics of the trench are improved. For example, an oxide film formed in the trench has high quality, whereby a gate withstanding voltage is improved.
摘要翻译： 半导体衬底具有用于在其中形成栅极绝缘膜和栅电极的沟槽，或者与其他元件隔离半导体元件如晶体管的绝缘隔离。 沟槽由各向异性干蚀刻形成。 之后，使用含有氢氟酸和硝酸的混合溶液，通过湿法将沟槽的形状改善，使得底部和开口部分成圆形或锥形。 通过改变沟槽的形状，改善了沟槽的电特性。 例如，形成在沟槽中的氧化膜具有高质量，从而提高了栅极耐压。
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