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    Electric compressor
    1.
    发明授权
    Electric compressor 有权
    电动压缩机

    公开(公告)号：US08231365B2

    公开(公告)日：2012-07-31

    申请号：US12159775

    申请日：2006-12-27

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： F04B35/04 ,  H02K5/24 ,  H02K11/00 ,  H01R13/627 ,  H01R4/38 ,  H01R13/648

    CPC分类号： F04C23/008 ,  F04C18/0215 ,  F04C2240/803 ,  H01R33/973 ,  H02K5/225 ,  H02K7/14

    摘要： An electric compressor includes a built-in electric motor for driving the compressor and a connection section between an external terminal for power supply to the electric motor and the end of a wire from a stator of the electric motor and is stored in a compressor housing. The connection section is constructed from a housing side coupler engaged with the compressor housing, a power supply-external terminal side coupler engaged with the housing side coupler, and a stator side coupler for holding the end of the wire from the stator, fitted to the power supply-external terminal side coupler, and engaged with the housing side coupler. Vibration resistance of a terminal connection section for the motor is improved and breakage and momentary electrical interruption at the terminal connection section may be prevented, with productivity of the compressor maintained at a good level.

    摘要翻译： 电动压缩机包括内置的电动机，用于驱动压缩机，以及在电动机的电源供给的外部端子与来自电动机的定子的电线的端部之间的连接部，并存储在压缩机壳体中。 连接部分由与压缩机壳体接合的壳体侧联接器，与壳体侧联接器啮合的电源 - 外部端子侧联接器和用于将电线的端部固定在定子上的定子侧联接器构成， 电源 - 外部端子侧耦合器，并与壳体侧耦合器接合。 电动机的端子连接部的耐振性得到改善，并且可以防止端子连接部断裂和瞬间的电中断，同时压缩机的生产率保持在良好的水平。

    ELECTRIC COMPRESSOR
    2.
    发明申请
    ELECTRIC COMPRESSOR 有权
    电动压缩机

    公开(公告)号：US20090269221A1

    公开(公告)日：2009-10-29

    申请号：US12159775

    申请日：2006-12-27

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： F04B17/03 ,  F04B17/00

    CPC分类号： F04C23/008 ,  F04C18/0215 ,  F04C2240/803 ,  H01R33/973 ,  H02K5/225 ,  H02K7/14

    摘要： An electric compressor having a built-in electric motor for driving the compressor and in which a connection section between an external terminal for power supply to the electric motor and the end of a wire from a stator of the electric motor is stored in a compressor housing. The electric compressor is characterized in that the connection section is constructed from a housing side coupler engaged with the compressor housing, a power supply-external terminal side coupler engaged with the housing side coupler, and a stator side coupler for holding the end of the wire from the stator, fitted to the power supply-external terminal side coupler, and engaged with the housing side coupler. In this electric compressor, vibration resistance of a terminal connection section for the motor is improved and breakage and momentary electrical interruption at the terminal connection section can be prevented, with productivity of the compressor maintained at a good level.

    摘要翻译： 一种具有用于驱动压缩机的内置电动马达的电动压缩机，其中，将电动机的电力供给用的外部端子与电动机的定子的电线的端部之间的连接部分储存在压缩机壳体 。 电动压缩机的特征在于，连接部分由与压缩机壳体接合的壳体侧联接器，与壳体侧联接器啮合的电源 - 外部端子侧联接器和用于保持电线端部的定子侧连接器构成 从定子安装到电源 - 外部端子侧耦合器，并与壳体侧耦合器接合。 在该电动压缩机中，由于压缩机的生产率维持在良好的水平，所以能够提高电动机的端子连接部的耐振动性，能够防止端子连接部的断裂和瞬间的电中断。

    Nonvolatile semiconductor memory device with memory cells, each having an FG cell transistor and select gate transistor, and a method of writing data into the same
    3.
    发明授权
    Nonvolatile semiconductor memory device with memory cells, each having an FG cell transistor and select gate transistor, and a method of writing data into the same 失效
    具有存储单元的非易失性半导体存储器件，每个具有FG单元晶体管和选择栅极晶体管，以及将数据写入其中的方法

    公开(公告)号：US07339828B2

    公开(公告)日：2008-03-04

    申请号：US11248303

    申请日：2005-10-13

    申请人： Takehiro Hasegawa ,  Susumu Shuto

    发明人： Takehiro Hasegawa ,  Susumu Shuto

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0425 ,  G11C16/10

    摘要： A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the source of the cell transistor and whose source is connected to a source line. The source line driver is configured so as to drive the source line in a write operation at a potential between the substrate bias potential of the cell transistor and select gate transistor and the ground potential.

    摘要翻译： 半导体器件包括存储单元阵列和源极线驱动器。 存储单元阵列中的每个存储单元具有浮置单元晶体管，其通过在浮置栅极中累积电荷来存储数据;以及选择栅极晶体管，其漏极连接到单元晶体管的源极，源极连接到源极 线。 源极线驱动器被配置为在写入操作中以单电池晶体管的衬底偏置电位和选择栅极晶体管的电位与地电位之间的电位驱动源极线。

    Semiconductor memory device including MOS transistors each having a floating gate and a control gate
    4.
    发明授权
    Semiconductor memory device including MOS transistors each having a floating gate and a control gate 失效
    半导体存储器件包括各自具有浮置栅极和控制栅极的MOS晶体管

    公开(公告)号：US07312503B2

    公开(公告)日：2007-12-25

    申请号：US10753324

    申请日：2004-01-09

    申请人： Akira Umezawa ,  Takehiro Hasegawa

    发明人： Akira Umezawa ,  Takehiro Hasegawa

    IPC分类号： H01L29/76 ,  H01L31/062

    CPC分类号： H01L27/11526 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.

    摘要翻译： 半导体存储器件包括多个存储单元，多个局部位线，全局位线，第一开关元件和保持电路。 存储单元包括第一和第二MOS晶体管。 第一MOS晶体管具有电荷累积层和控制栅极。 第二MOS晶体管的电流路径的一端连接到第一MOS晶体管的电流路径的一端。 局部位线连接第一MOS晶体管的电流路径的另一端。 第一个开关元件在本地位线和全局位线之间建立连接。 保持电路连接到全局位线，并保存要写入存储单元的数据。

    Nonvolatile semiconductor memory device with memory cells, each having an FG cell transistor and select gate transistor, and a method of writing data into the same
    5.
    发明申请
    Nonvolatile semiconductor memory device with memory cells, each having an FG cell transistor and select gate transistor, and a method of writing data into the same 失效
    具有存储单元的非易失性半导体存储器件，每个具有FG单元晶体管和选择栅极晶体管，以及将数据写入其中的方法

    公开(公告)号：US20060083066A1

    公开(公告)日：2006-04-20

    申请号：US11248303

    申请日：2005-10-13

    申请人： Takehiro Hasegawa ,  Susumu Shuto

    发明人： Takehiro Hasegawa ,  Susumu Shuto

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0425 ,  G11C16/10

    摘要： A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the source of the cell transistor and whose source is connected to a source line. The source line driver is configured so as to drive the source line in a write operation at a potential between the substrate bias potential of the cell transistor and select gate transistor and the ground potential.

    摘要翻译： 半导体器件包括存储单元阵列和源极线驱动器。 存储单元阵列中的每个存储单元具有浮置单元晶体管，其通过在浮置栅极中累积电荷来存储数据;以及选择栅极晶体管，其漏极连接到单元晶体管的源极，源极连接到源极 线。 源极线驱动器被配置为在写入操作中以单电池晶体管的衬底偏置电位和选择栅极晶体管的电位与地电位之间的电位驱动源极线。

    Terminal connection structure of motor incorporated within a compressor
    6.
    发明申请
    Terminal connection structure of motor incorporated within a compressor 有权
    压缩机内装有电机的端子连接结构

    公开(公告)号：US20060068626A1

    公开(公告)日：2006-03-30

    申请号：US11229723

    申请日：2005-09-20

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： H01R13/52

    CPC分类号： H01R13/521 ,  F04C29/0085 ,  F04C2240/803 ,  H01R13/5202 ,  H02K5/225

    摘要： A terminal connection structure of a motor incorporated within a compressor for connecting feed terminals for a stator of a motor to the compressor includes a lid, which is attached to a compressor body portion for securing external feed terminals with a hermetic seal. The terminal connection structure is provided with a resin chamber on an inner surface of the lid, through which the external feed terminals extend, and a resin housing containing wire-side terminals, which are provided at ends of wires connected to the stator and which are connected to the external feed terminals. In the structure, superior insulation properties may be obtained even if the compressor size is reduced, and the productivity and assembling performance of the compressor may be improved.

    摘要翻译： 并入用于将电动机的定子的供给端子连接到压缩机的电动机的端子连接结构包括：盖，其附接到压缩机主体部分，用于固定具有气密密封的外部进给端子。 端子连接结构在盖的内表面上设置有树脂室，外部馈电端子延伸穿过该树脂室，并且包括线侧端子的树脂壳体设置在连接到定子的导线的端部， 连接到外部馈电端子。 在该结构中，即使压缩机尺寸减小也可以获得优异的绝缘性能，并且可以提高压缩机的生产率和组装性能。

    Semiconductor memory device including MOS transistors each having a floating gate and a control gate
    7.
    发明授权
    Semiconductor memory device including MOS transistors each having a floating gate and a control gate 有权
    半导体存储器件包括各自具有浮置栅极和控制栅极的MOS晶体管

    公开(公告)号：US06937514B2

    公开(公告)日：2005-08-30

    申请号：US10647242

    申请日：2003-08-26

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524

    摘要： A semiconductor memory device includes a plurality of memory cells, a memory cell array, bit lines, word lines, select gate lines, a column decoder, a first row decoder, a second row decoder, and first metal wiring. The memory cell includes a first MOS transistor with a charge accumulation layer and a control gate and a second MOS transistor connected to the first MOS transistor. The memory cell array has the memory cells arranged in a matrix. The word line connects commonly the control gates in the same row. The select gate line connects commonly the gates of the second MOS transistors in the same row. The first metal wiring layers are provided for every select gate lines, and pass through almost the central part of the memory cells. The first metal wiring layer is connected electrically to one of the select gate lines.

    摘要翻译： 半导体存储器件包括多个存储器单元，存储单元阵列，位线，字线，选择栅极线，列解码器，第一行解码器，第二行解码器和第一金属布线。 存储单元包括具有电荷累积层的第一MOS晶体管和连接到第一MOS晶体管的控制栅极和第二MOS晶体管。 存储单元阵列具有排列成矩阵的存储单元。 字线通常连接在同一行中的控制门。 选择栅极线共同连接同一行中的第二MOS晶体管的栅极。 为每个选择栅极线设置第一金属布线层，并且几乎通过存储单元的中心部分。 第一金属布线层电连接到选择栅极线之一。

    Semiconductor chip with fuse unit
    9.
    发明授权
    Semiconductor chip with fuse unit 失效
    半导体芯片带保险丝单元

    公开(公告)号：US06818957B2

    公开(公告)日：2004-11-16

    申请号：US10178748

    申请日：2002-06-25

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： H01L2976

    CPC分类号： H01L23/5258 ,  G11C17/18 ,  G11C29/802 ,  H01L23/5256 ,  H01L24/02 ,  H01L24/10 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.

    摘要翻译： 半导体芯片包括逻辑电路单元，至少一个具有恢复缺陷单元的冗余存储单元的存储器宏单元，布置在逻辑电路单元外部的电极焊盘行和存储器宏单元，以及至少一个保险丝 单元组存储缺陷单元的地址，并且布置在沿着半导体芯片的任何边缘的区域中，并且在逻辑电路单元的外部，存储宏单元和电极垫行。 这里，逻辑电路单元，存储器宏单元，电极焊盘列和熔丝单元组位于半导体芯片表面上。

    Semiconductor integrated circuit device with electrically programmable fuse
    10.
    发明授权
    Semiconductor integrated circuit device with electrically programmable fuse 失效

    公开(公告)号：US06542419B2

    公开(公告)日：2003-04-01

    申请号：US09934834

    申请日：2001-08-23

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： G11C700

    CPC分类号： G11C29/785 ,  G11C17/18

    摘要： A fuse circuit 1 comprises an electrically programmable fuse 10 and a data latch circuit 11 to hold programmed fuse data. In the data latch circuit 11, prior to programming, a node FUADD is precharged to “H” by a precharge circuit 14 and preset at “H” as the result of the logical product of a fail address FAADD and a latch signal LATCHp by a preset circuit 12 when the fuse 10 needs to be programmed. A programming selecting circuit 13 monitors the node FUADD to select whether to perform or not to performance the programming of the fuse 10. Accordingly, efficient electric programming control becomes possible without using a dedicated register to hold a fuse address to be programmed.