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    TERMINAL DEVICE FOR ELECTRIC COMPRESSOR
    3.
    发明申请
    TERMINAL DEVICE FOR ELECTRIC COMPRESSOR 审中-公开
    电动压缩机终端装置

    公开(公告)号：US20100247346A1

    公开(公告)日：2010-09-30

    申请号：US12739582

    申请日：2008-10-21

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： F04B35/04 ,  H01R13/52

    CPC分类号： F04C23/008 ,  F04C2240/803

    摘要： Provided is a terminal device for an electric compressor in which each inputting female terminal of a cluster holding a plurality of inputting female terminals for input into an electric motor built in a compressor in a resin housing is engaged with the inner end of each sealed terminal of a sealed terminal device. The terminal device is characterized in that a resin housing storing section for storing the resin housing is formed in a compressor housing, and in that the resin housing stored in the resin housing storing section is clamped between the compressor housing and a terminal plate of the sealed terminal device mounted on the compressor housing. The terminal device can prevent coming off of the inputting female terminal and undesired positional shifting of the resin housing, and can improve its assembling ability.

    摘要翻译： 提供一种电动压缩机的终端装置，其中，保持多个输入母端子的群的每个输入母端子被输入到内置在树脂壳体中的压缩机中的电动马达与每个密封端子的内端接合 一个密封的终端设备。 端子装置的特征在于，在压缩机壳体中形成有用于储存树脂壳体的树脂容纳部分储存部分，并且存储在树脂容纳部分中的树脂壳体夹在压缩机壳体和密封的端子板之间 终端设备安装在压缩机壳体上。 终端装置可以防止输入母端子的脱落和树脂壳体的不期望的位置偏移，并且可以提高其组装能力。

    Terminal connection structure of motor incorporated within a compressor
    4.
    发明授权
    Terminal connection structure of motor incorporated within a compressor 有权
    压缩机内装有电机的端子连接结构

    公开(公告)号：US07344400B2

    公开(公告)日：2008-03-18

    申请号：US11229723

    申请日：2005-09-20

    申请人： Takehiro Hasegawa

    发明人： Takehiro Hasegawa

    IPC分类号： H01R13/52

    CPC分类号： H01R13/521 ,  F04C29/0085 ,  F04C2240/803 ,  H01R13/5202 ,  H02K5/225

    摘要： A terminal connection structure of a motor incorporated within a compressor for connecting feed terminals for a stator of a motor to the compressor includes a lid, which is attached to a compressor body portion for securing external feed terminals with a hermetic seal. The terminal connection structure is provided with a resin chamber on an inner surface of the lid, through which the external feed terminals extend, and a resin housing containing wire-side terminals, which are provided at ends of wires connected to the stator and which are connected to the external feed terminals. In the structure, superior insulation properties may be obtained even if the compressor size is reduced, and the productivity and assembling performance of the compressor may be improved.

    摘要翻译： 并入用于将电动机的定子的供给端子连接到压缩机的电动机的端子连接结构包括：盖，其附接到压缩机主体部分，用于固定具有气密密封的外部进给端子。 端子连接结构在盖的内表面上设置有树脂室，外部馈电端子延伸穿过该树脂室，并且包括线侧端子的树脂壳体设置在连接到定子的导线的端部， 连接到外部馈电端子。 在该结构中，即使压缩机尺寸减小也可以获得优异的绝缘性能，并且可以提高压缩机的生产率和组装性能。

    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate
    5.
    发明授权
    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate 失效
    具有包括浮动栅极和控制栅极的堆叠栅极的半导体集成电路器件

    公开(公告)号：US07332766B2

    公开(公告)日：2008-02-19

    申请号：US11083156

    申请日：2005-03-18

    申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

    摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

    摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

    Vibrating type compressor
    6.
    发明授权
    Vibrating type compressor 有权
    振动式压缩机

    公开(公告)号：US06994530B2

    公开(公告)日：2006-02-07

    申请号：US10415030

    申请日：2001-10-23

    申请人： Yoshiaki Fujisawa ,  Takehiro Hasegawa

    发明人： Yoshiaki Fujisawa ,  Takehiro Hasegawa

    IPC分类号： F04B35/04

    CPC分类号： H02K33/18 ,  F04B35/045 ,  H02K1/34

    摘要： A vibration type compressor related to the present invention, in which a compressor main body 3 is built into a gastight vessel 2 including a yoke 7-1, a magnetic path member 7 formed from a column-shaped core pole 7-2, a permanent magnet 12 arranged in the magnetic path, an electromagnetic coil 14 which is arranged within an annular magnetic gap 13 between the magnetic path members 7 by being supported by a mechanical vibration system to as to be able to vibrate and is wound around a lead plate to perform the connection treatment of a terminal thereof, a piston 16 connected to the electromagnetic coil 14, and a cylinder block 8 which closes the yoke 7-1 and in the interior of which is formed the cylinder portion 17 housing the piston 16, characterized in that the permanent magnet 12 is formed from a neodymium magnet or a rare-earth magnet and in that the cylindrical permanent magnet 12 is divided into four parts in the axial direction thereof, the four-part divided magnet being bonded and fixed to the side of the core pole 7-2, whereby the vibration type compressor is miniaturized and its efficiency is increased.

    摘要翻译： 本发明的振动型压缩机，其特征在于，压缩机主体3内置有包括轭架7的气密容器2，由柱状芯棒7-2形成的磁路部件7，永磁体 布置在磁路中的磁体12，电磁线圈14，其布置在磁路构件7之间的环形磁隙13内，由机械振动系统支撑，以便能够振动并卷绕在引线板上 执行其端子的连接处理，连接到电磁线圈14的活塞16以及闭合轭7-1并且其内部形成有容纳活塞16的气缸部17的气缸体8，其特征在于， 永磁体12由钕磁体或稀土类磁体形成，圆柱形永久磁铁12的轴向分为四部分，四部分分磁铁为 粘结并固定在芯柱7-2的侧面，由此使振动式压缩机小型化，效率提高。

    Semiconductor memory device having a power-down mode
    8.
    发明授权
    Semiconductor memory device having a power-down mode 失效
    具有掉电模式的半导体存储器件

    公开(公告)号：US6088290A

    公开(公告)日：2000-07-11

    申请号：US132644

    申请日：1998-08-11

    申请人： Hiroyuki Ohtake ,  Shigeo Ohshima ,  Takehiro Hasegawa

    发明人： Hiroyuki Ohtake ,  Shigeo Ohshima ,  Takehiro Hasegawa

    IPC分类号： G11C11/413 ,  G11C7/20 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/20

    摘要： When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.

    摘要翻译： 当与时钟信号异步的时钟使能信号被设置为高电平时，掉电控制电路将掉电信号设置在高电平以释放掉电模式。 当释放掉电模式时，时钟控制电路输出内部时钟信号，使得可以锁存命令解码器的输出信号。 根据这样的结构，可以减少在释放掉电模式之后的命令的锁存到命令可以传送的时间段，并且可以实现高速操作。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5615163A

    公开(公告)日：1997-03-25

    申请号：US598706

    申请日：1996-02-08

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Semiconductor memory
    10.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5463577A

    公开(公告)日：1995-10-31

    申请号：US365104

    申请日：1994-12-28

    申请人： Yukihito Oowaki ,  Takehiro Hasegawa

    发明人： Yukihito Oowaki ,  Takehiro Hasegawa

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C8/14 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404 ,  G11C11/407 ,  G11C11/24

    CPC分类号： G11C8/12 ,  G11C8/14

    摘要： There is provided a semiconductor memory having a reduced power consumption in data access and a high access speed in a NAND cell array scheme in which a memory cell unit is constituted by cascade-connecting a plurality of memory cells with each other. A memory cell array is divided into a plurality of sub-arrays, and the divided sub-arrays are selectively activated, thereby decreasing the capacitances of the word lines, register word lines, bit lines, and the like which are charged/discharged in data access.

    摘要翻译： 提供了一种在NAND单元阵列方案中数据访问中具有降低的功耗以及高存取速度的半导体存储器，其中通过将多个存储单元彼此级联连接而构成存储单元单元。 存储单元阵列被分成多个子阵列，并且分割的子阵列被选择性地激活，从而减少在数据中被充电/放电的字线，寄存器字线，位线等的电容 访问。