公开(公告)号：US20060024444A1

公开(公告)日：2006-02-02

申请号：US10900501

申请日：2004-07-28

申请人： Thomas Brody

发明人： Thomas Brody

IPC分类号： B05D1/32 ,  B05C11/11 ,  B05D1/40

CPC分类号： C23C14/042 ,  C23C14/562 ,  H01L51/0011

摘要： The present invention is a two-layer shadow mask with small dimension apertures and method of making and using same. The two-layer shadow mask of the present invention is suitable for use for manufacturing an electronic device via deposition in a production system. The two-layer shadow mask of the present invention is formed by a first thick mask, which includes a plurality of apertures that has been formed, for example, by etching, bonded to a second, comparatively thin mask, that has been formed by an electrolytic process, and which includes a plurality of apertures that has been patterned by a photoresist. The second mask is aligned and bonded atop the first mask, with their respective apertures desirably offset one to another. The offset amount of the respective apertures of the two-layer shadow mask determines the resulting final aperture dimension, which may approach 0 microns, through which material is deposited upon a substrate in a deposition production system.

公开(公告)号：US20070068559A1

公开(公告)日：2007-03-29

申请号：US11236937

申请日：2005-09-27

申请人： Thomas Brody

发明人： Thomas Brody

IPC分类号： B08B1/02 ,  B08B6/00 ,  H01L21/84 ,  B05D1/32

CPC分类号： C23C14/042 ,  B08B7/0035 ,  B08B13/00 ,  C23C14/564 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/78681 ,  H01L51/0011

摘要： Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.

摘要翻译： 电子器件形成在通过多个沉积容器逐步前进的衬底上。 每个沉积容器包括沉积材料源并且具有与其相关联的至少两个荫罩。 两个掩模中的每一个交替地位于相应的沉积容器内，用于通过位于其中的掩模中的孔将沉积材料图案化到衬底上，并且定位在邻近的清洁容器中以进行掩模清洁。 同时执行图案化到基板上以及清洁至少一个掩模。

公开(公告)号：US20070051311A1

公开(公告)日：2007-03-08

申请号：US11593382

申请日：2006-11-06

申请人： Thomas Brody ,  Joseph Marcanio ,  Jeffrey Conrad ,  Timothy Cowen

发明人： Thomas Brody ,  Joseph Marcanio ,  Jeffrey Conrad ,  Timothy Cowen

IPC分类号： C23C16/00

CPC分类号： H05K3/467 ,  H01L21/67173 ,  H01L21/67207 ,  H05K1/0393 ,  H05K3/143 ,  H05K3/4076 ,  H05K2203/1545 ,  Y10S438/944 ,  Y10S438/945

摘要： Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its edge. The second insulator layer is then deposited on another portion of the first conductor layer in a manner whereupon the second insulator layer slightly overlaps each notch of the first insulator layer, thereby forming the one or more via holes. A conductive filler can optionally be deposited in each via hole. Lastly, a second conductive layer can be deposited over the first insulator layer, the second insulator layer and, if provided, the conductive filler.

摘要翻译： 通过沉积第一导体层并随后在第一导体层的一部分上沉积第一绝缘体层，在连续的在线荫罩制备系统中形成通孔。 以沿其边缘限定至少一个凹口的方式沉积第一绝缘体层。 然后以第二绝缘体层与第一绝缘体层的每个凹口稍微重叠的方式将第二绝缘体层沉积在第一导体层的另一部分上，从而形成一个或多个通孔。 可以任选地在每个通孔中沉积导电填料。 最后，第二导电层可以沉积在第一绝缘体层，第二绝缘体层上，如果提供，则沉积在导电填料上。

公开(公告)号：US20060021869A1

公开(公告)日：2006-02-02

申请号：US10900620

申请日：2004-07-28

申请人： Thomas Brody

发明人： Thomas Brody

IPC分类号： C23C14/00 ,  C23C14/32

CPC分类号： C23C14/042 ,  C23C14/562

摘要： A deposition system uses the same low coefficient of thermal expansion (CTE) material, for example, a CTE of below 10 ppm/° C. in the temperature range of 0-200° C., for forming both a shadow mask and a substrate upon which depositions occur in order to overcome the heating effects of a high-temperature deposition process, thereby ensuring a uniform expansion and contraction rate of the shadow mask and the substrate.

摘要翻译： 沉积系统在0-200℃的温度范围内使用相同的低热膨胀系数（CTE）材料，例如低于10ppm /℃的CTE，用于形成荫罩和基底 发生沉积以克服高温沉积工艺的加热效果，从而确保荫罩和基板的均匀的膨胀和收缩率。

公开(公告)号：US20060281206A1

公开(公告)日：2006-12-14

申请号：US11147508

申请日：2005-06-08

申请人： Thomas Brody

发明人： Thomas Brody

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  C23C14/042 ,  C23C14/562 ,  H01L27/1214 ,  H01L27/14683 ,  Y10S438/944

摘要： A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

摘要翻译： 阴影掩模沉积系统包括多个相同的阴影掩模，其布置在多个堆叠中以形成相同数量的复合荫罩，每个复合荫罩与材料沉积源一起设置在沉积真空容器中。 来自材料沉积源的材料通过相应的复合阴影掩模中的开口沉积在基板上，每个开口由形成复合荫罩的阴影掩模中的孔的整体或部分对准形成，以形成电子元件阵列 基质。

公开(公告)号：US20060141763A1

公开(公告)日：2006-06-29

申请号：US11044140

申请日：2005-01-27

申请人： Thomas Brody ,  Joseph Marcanio

发明人： Thomas Brody ,  Joseph Marcanio

IPC分类号： H01L21/4763

CPC分类号： H01L21/768 ,  H01L21/6715 ,  H01L21/67173 ,  H01L21/67207 ,  H01L21/76802 ,  H05K1/0393 ,  H05K3/143 ,  H05K3/4076 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2203/1545

摘要： A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).

摘要翻译： 多层电子器件可以形成为在绝缘基板（212）上包括绝缘基板（212），第一蒸镀导体层（312），第一导体层上的第一蒸镀绝缘体层（314） 312），其中具有至少一个通孔（316）的第一绝缘体层（314）和在第一绝缘体层（314）的通孔（316）中的气相沉积导电填料（320）。 期望地，导电填料（320）沉积在第一绝缘体层（314）的通孔（316）中，使得与第一导体层（312）相对的导电填料（320）的表面与表面 与第一导体层（312）相对的第一绝缘体层（314）。

公开(公告)号：US20070246706A1

公开(公告)日：2007-10-25

申请号：US11820659

申请日：2007-06-20

申请人： Thomas Brody

发明人： Thomas Brody

IPC分类号： H01L29/06 ,  H01L21/06 ,  H01L33/00

CPC分类号： H01L27/1288 ,  C23C14/042 ,  C23C14/562 ,  H01L27/1214 ,  H01L27/14683 ,  Y10S438/944

摘要： An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.

摘要翻译： 具有通过荫罩气相沉积形成的重复图案的电子电路包括形成在基板上的电子电路元件的重复图案。 每个电子电路元件以期望的沉积顺序包括以下元件：第一半导体段，第二半导体段，第一金属段，第二金属段，第三金属段，第四金属段，第五金属段， 第六金属段，第一绝缘体段，第二绝缘体段，第三绝缘体段，第七金属段，第八金属段，第九金属段和第十金属段。 所有上述段可以通过荫罩沉积工艺沉积。 电子电路元件可以是类似电子电路元件的阵列的元件。

公开(公告)号：US20070243719A1

公开(公告)日：2007-10-18

申请号：US11820406

申请日：2007-06-19

申请人： Thomas Brody

发明人： Thomas Brody

IPC分类号： H01L21/31 ,  C23C14/00 ,  H01L21/027

CPC分类号： H01L27/1288 ,  C23C14/042 ,  C23C14/562 ,  H01L27/1214 ,  H01L27/14683 ,  Y10S438/944

摘要： A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

摘要翻译： 阴影掩模沉积系统包括多个相同的阴影掩模，其布置在多个堆叠中以形成相同数量的复合荫罩，每个复合荫罩与材料沉积源一起设置在沉积真空容器中。 来自材料沉积源的材料通过相应的复合阴影掩模中的开口沉积在基板上，每个开口由形成复合荫罩的阴影掩模中的孔的整体或部分对准形成，以形成电子元件阵列 基质。

公开(公告)号：US20070235731A1

公开(公告)日：2007-10-11

申请号：US11764703

申请日：2007-06-18

申请人： Thomas Brody ,  Paul Malmberg ,  Joseph Marcanio

发明人： Thomas Brody ,  Paul Malmberg ,  Joseph Marcanio

IPC分类号： H01L51/56 ,  H01L51/52

CPC分类号： C23C14/562 ,  C23C14/042 ,  C23C14/541 ,  H01L51/0008 ,  H01L51/0023 ,  H01L51/529 ,  H01L51/56 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for providing an active array of temperature sensing and cooling elements, including an active heatsink which further includes an active temperature sensing layer, a thermoelectric cooling layer, and a heatsink, which further includes a plurality of cooling channels. The temperature sensing element within the active temperature sensing layer includes a plurality of switching transistors, a linear transistor, a current sense resistor, a thermistor, a voltage sensing bus, a voltage setting bus, a current measurement bus, a measurement switching bus, a sense control bus, a storage capacitor, and a supply voltage, all under the control of a process control computer. The method of using an active array of temperature sensing and cooling elements includes the steps of aligning the shadow mask, depositing the material, detecting a thermal gradient, and controlling the thermoelectric cooling.

摘要翻译： 一种用于提供温度感测和冷却元件的有源阵列的系统和方法，包括有源散热器，其还包括有源温度感测层，热电冷却层和散热器，其还包括多个冷却通道。 有源温度检测层内的温度检测元件包括多个开关晶体管，线性晶体管，电流检测电阻，热敏电阻，电压感测总线，电压设定总线，电流测量总线，测量开关总线， 感测控制总线，存储电容器和电源电压，全部由过程控制计算机控制。 使用温度感测和冷却元件的有源阵列的方法包括对准荫罩，沉积材料，检测热梯度和控制热电冷却的步骤。

公开(公告)号：US20060152641A1

公开(公告)日：2006-07-13

申请号：US11032416

申请日：2005-01-10

申请人： Thomas Brody

发明人： Thomas Brody

IPC分类号： G02F1/1343

CPC分类号： G02F1/1362 ,  G02F2001/136231 ,  H01L27/1288

摘要： An LCD pixel includes a first conductive segment connected to a first bus, a first insulator segment on the first conductive segment, a second conductive segment on the first insulator segment, a liquid crystal material on the second conductive segment, a third conductive segment on the liquid crystal material, and a thin film transistor having a control terminal, a first power terminal and second power terminal connected to a second bus, a third bus and the second conductive segment, respectively. In response to application of a suitable signal on the second bus when reference voltages are present on the first bus and on the third conductive segment, and a voltage is applied to the third bus, the thin film transistor is operative for charging a capacitor formed by the first conductive segment, the first insulator segment and the second conductive segment and for activating the liquid crystal material.