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公开(公告)号：US4348741A
公开(公告)日：1982-09-07
申请号：US169558
申请日：1980-07-17
CPC分类号： G06F7/74 , G06F9/30043 , H03M11/02
摘要： Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel output is also fed back to reset its associated latch to permit the channel of next highest priority to generate an output.
摘要翻译： 优先编码器寄存器的每个通道配备有用于存储二进制数据字的一位的锁存器。 最高优先级的信道产生应用于编码装置的输出，该编码装置又产生唯一的码。 信道输出也被反馈以复位其相关联的锁存器，以允许下一个最高优先级的信道生成输出。
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公开(公告)号：US4296469A
公开(公告)日：1981-10-20
申请号：US961798
申请日：1978-11-17
CPC分类号： G06F15/7832 , G06F9/38
摘要： A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits. Serial bus switches on each of two parallel buses allow concatenation with a second pair of buses. Each bus, while 16 bits wide, actually utilizes two conductors per bit to carry data and the complement thereof.
摘要翻译： 具有执行单元的数据处理器采用分段总线结构和双端口寄存器单元，以便增加电路密度并且允许地址和数据计算同时发生。 该电路设计为与外部16位双向数据总线和具有多达32个地址位的外部地址总线进行接口。 两个并行总线中的每个串行总线开关允许与第二对总线连接。 每个总线，而16位宽，实际上每位使用两个导体来承载数据及其补码。
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3.发明授权High speed TTL clock input buffer circuit which minimizes power and provides CMOS level translation 失效高速TTL时钟输入缓冲电路，最大限度地降低功耗并提供CMOS电平转换
公开(公告)号：US4578601A
公开(公告)日：1986-03-25
申请号：US559070
申请日：1983-12-07
IPC分类号： H03K19/017 , H03K19/0185 , H03K19/096
CPC分类号： H03K19/018521 , H03K19/01707
摘要： A buffer circuit is provided for buffering an input clock signal having TTL voltage levels to provide an output clock signal having MOS voltage levels. A reference voltage portion provides an accurate bias voltage to a first node. A voltage translation portion is coupled between an input and the first node. An inverter portion has a first input connected to the first node, a second input for receiving the input clock signal, and an output for providing the output clock signal. A clamping portion is connected to the first node to minimize the bias voltage potential.
摘要翻译： 提供缓冲电路用于缓冲具有TTL电压电平的输入时钟信号，以提供具有MOS电压电平的输出时钟信号。 参考电压部分向第一节点提供精确的偏置电压。 电压转换部分耦合在输入端和第一节点之间。 逆变器部分具有连接到第一节点的第一输入端，用于接收输入时钟信号的第二输入端和用于提供输出时钟信号的输出端。 钳位部分连接到第一节点以最小化偏置电压电位。
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公开(公告)号：US4663545A
公开(公告)日：1987-05-05
申请号：US672539
申请日：1984-11-15
CPC分类号： G11C8/08 , H03K3/012 , H03K3/356078
摘要： A state machine in which the next state signals are biased by the next state encoder very close to the switch voltage of the input transistors of the present state latches to improve the response time of the state machine. Charge sharing on the outputs of the next state selector is prevented from affecting the biased next state signals by voltage substaining circuitry. By pre-encoding input signals pertinent to each state using separate input logic, the size of the next state selector is minimized, further improving the response time of the state machine. Selected present state latches may be prevented from changing state by gating the next state signals.
摘要翻译： 一种状态机，其中下一个状态信号被非常接近当前状态的输入晶体管的开关电压的下一个状态编码器偏置，以改善状态机的响应时间。 防止下一个状态选择器的输出上的电荷共享通过电压分配电路影响偏置的下一个状态信号。 通过使用单独的输入逻辑预编码与每个状态相关的输入信号，使下一状态选择器的大小最小化，进一步提高状态机的响应时间。 可以通过选通下一状态信号来防止选定的当前状态锁存器改变状态。
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公开(公告)号：US4318014A
公开(公告)日：1982-03-02
申请号：US61334
申请日：1979-07-27
IPC分类号： G11C17/12 , G11C17/14 , H03K19/096 , G11C8/02
摘要： A read-only-memory circuit is disclosed which includes a plurality of column conductors and circuitry for selecting one of the plurality of column conductors in response to an input address. The selection circuitry couples each of the column conductors to a common node which is coupled to a precharge circuit such that only the selected column conductor is precharged. The precharged circuit includes first and second diode-connected IGFET devices coupled in series such that the first IGFET device is a standard enhancement mode transistor which includes an implanted channel while the second IGFET device is a natural transistor which does not include an implanted channel.
摘要翻译： 公开了一种只读存储器电路，其包括多个列导体和用于响应于输入地址选择多个列导体之一的电路。 选择电路将每个列导体耦合到公共节点，该公共节点耦合到预充电电路，使得仅选择的列导体被预充电。 预充电电路包括串联耦合的第一和第二二极管连接的IGFET器件，使得第一IGFET器件是包括注入通道的标准增强型晶体管，而第二IGFET器件是不包括注入通道的自然晶体管。
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公开(公告)号：US4292547A
公开(公告)日：1981-09-29
申请号：US61206
申请日：1979-07-27
IPC分类号： G11C11/34 , G11C8/00 , G11C8/10 , G11C11/408 , H03K19/0944 , H03K19/096 , H03K19/094 , H01L29/52
CPC分类号： G11C8/10 , G11C11/4087 , H03K19/09441 , H03K19/096
摘要： A decoder circuit suitable for integrated circuit implementation using IGFET processing is disclosed which may be implemented in a highly dense structure. The decoder output lines are grouped in pairs and at least one of the output lines in each pair is discharged as determined by a bit in the input address. A plurality of IGFET devices under the control of the remaining input address bits selectively couple together the two output lines in each pair such that both output lines can then become discharged. Series-coupled pairs of IGFET devices are used in place of a single IGFET device in order to reduce the chip area required to implement the decoder structure.
摘要翻译： 公开了一种适用于使用IGFET处理的集成电路实现的解码器电路，其可以以高密度结构来实现。 解码器输出线成对分组，并且每对输出线中的至少一个输出线由输入地址中的位确定放电。 在剩余的输入地址位的控制下的多个IGFET器件选择性地将每一对中的两个输出线耦合在一起，使得两条输出线然后可以被放电。 使用串联耦合的IGFET器件对代替单个IGFET器件，以便减少实现解码器结构所需的芯片面积。
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