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    Method, system, and apparatus for adjacent-symbol error correction and detection code
    3.
    发明授权
    Method, system, and apparatus for adjacent-symbol error correction and detection code 有权
    用于相邻符号纠错和检测码的方法，系统和装置

    公开(公告)号：US08127213B2

    公开(公告)日：2012-02-28

    申请号：US11968148

    申请日：2007-12-31

    申请人： Thomas Holman

    发明人： Thomas Holman

    IPC分类号： H03M13/00

    CPC分类号： G11B20/1833 ,  G06F11/1028

    摘要： A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases. In an embodiment, a set of m bits of a first symbol and a set of m bits of a second symbol from a first set of data for transmission over a channel during a first clock phase are generated. A set of n bits of the first symbol and a set of n bits of the second symbol from a second set of data over a channel are also generated during a second clock phase. Other embodiments are also claimed and/or disclosed.

    摘要翻译： 一种用于基于在两个时钟相位中形成的相邻符号码字来产生纠错码（ECC）的电路和方法。 在一个实施例中，生成来自第一组数据的第一符号的m位的m位和第二符号的m位的集合，用于在第一时钟相位期间在信道上传输。 在第二时钟相位期间，还产生来自第一组数据的第一符号的n位和通道上的第二组数据的n位的一组n位。 还要求和/或公开其它实施例。

    Memory system anti-aliasing scheme
    7.
    发明申请
    Memory system anti-aliasing scheme 审中-公开
    内存系统抗锯齿方案

    公开(公告)号：US20070089032A1

    公开(公告)日：2007-04-19

    申请号：US11240823

    申请日：2005-09-30

    申请人： James Alexander ,  Joaquin Romera ,  Rajat Agarwal ,  Thomas Holman

    发明人： James Alexander ,  Joaquin Romera ,  Rajat Agarwal ,  Thomas Holman

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1024

    摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for a memory device anti-aliasing scheme. In an embodiment, a memory controller includes an error check agent to receive a codeword from a rank of memory and to provide an error indication in response to detecting a correctable adjacent-symbol-pair-error the rank of memory. An error counter may be coupled with the error check agent to increment towards a threshold value in response to the error indication from the error check agent. In an embodiment, a faulty memory device marker agent coupled with the error counter provides a faulty memory device marker to the error check agent, if the error counter exceeds the threshold value. Other embodiments are described and claimed.

    摘要翻译： 本发明的实施例一般涉及用于存储器件抗锯齿方案的系统，方法和装置。 在一个实施例中，存储器控制器包括错误检查代理，用于从存储器的等级接收码字，并且响应于检测存储器的等级的可校正的相邻符号对错误来提供错误指示。 响应于来自错误检查代理的错误指示，错误计数器可以与错误检查代理相结合以递增到阈值。 在一个实施例中，如果错误计数器超过阈值，则与错误计数器耦合的故障存储器设备标记代理向错误检查代理提供错误的存储器设备标记。 描述和要求保护其他实施例。