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    Methods and Apparatus for Designing and Constructing High-Speed Memory Circuits
    5.
    发明申请
    Methods and Apparatus for Designing and Constructing High-Speed Memory Circuits 审中-公开
    用于设计和构建高速存储器电路的方法和装置

    公开(公告)号：US20140104960A1

    公开(公告)日：2014-04-17

    申请号：US13651698

    申请日：2012-10-15

    申请人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

    发明人： Sundar Iyer ,  Shang-Tse Chuang ,  Thu Nguyen ,  Sanjeev Joshi ,  Adam Kablanian

    IPC分类号： G11C7/12 ,  G11C7/10

    CPC分类号： G11C7/12 ,  G11C7/1042 ,  G11C8/16 ,  G11C11/419

    摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store digital data bits. SRAM memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle. To handle memory operations faster, a bit line multiplexing system is proposed. Two sets of bit lines are coupled to each memory cell and each set of bit lines are used for memory operations in alternating memory cycles. During a first memory cycle, a first set of bit lines accesses the memory array while precharging a second set of bit lines. Then during a second memory cycle following the first memory cycle, the first set of bit lines are precharged while the second set of bit lines accesses the memory array to read data.

    摘要翻译： 在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数字数据位。 通常通过对地址进行解码来读取SRAM存储器电路，使用一组位线从寻址的存储器单元读取，从读取的存储器单元输出数据，并为后续存储器周期预充电位线。 为了更快地处理存储器操作，提出了一种位线复用系统。 两组位线耦合到每个存储器单元，并且每组位线用于交替存储器周期中的存储器操作。 在第一存储器周期期间，第一组位线在对第二组位线进行预充电的同时访问存储器阵列。 然后在第一存储器周期之后的第二存储器周期期间，第一组位线被预充电，而第二组位线访问存储器阵列以读取数据。

    Apparatus and method for testing of stacked die structure
    6.
    发明授权
    Apparatus and method for testing of stacked die structure 有权
    用于堆叠模具结构测试的装置和方法

    公开(公告)号：US08063654B2

    公开(公告)日：2011-11-22

    申请号：US12505215

    申请日：2009-07-17

    申请人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

    发明人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

    IPC分类号： G01R31/26

    CPC分类号： G01R31/318544 ,  H01L2224/16145

    摘要： An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.

    摘要翻译： 集成电路器件包括堆叠管芯和具有探针焊盘的基座，该探针焊盘直接耦合到基座芯片的测试逻辑，以实现用于集成电路器件测试的扫描链。 基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。 基座芯片还包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探测焊盘。 基准芯片的测试逻辑被配置为耦合到堆叠芯片的附加测试逻辑以实现扫描链。 探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来实现扫描链。

    Low power, small size SRAM architecture
    7.
    发明授权
    Low power, small size SRAM architecture 有权
    低功耗，小尺寸的SRAM架构

    公开(公告)号：US07764535B2

    公开(公告)日：2010-07-27

    申请号：US12137362

    申请日：2008-06-11

    申请人： Thu Nguyen

    发明人： Thu Nguyen

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413

    摘要： A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors coupled to ground. Each of the two NMOS transistors are coupled to one of the two PMOS transistors and are characterized by a second size substantially equal to the first size. The memory cell further includes two word line transistors coupled to a word line and characterized by a third size substantially equal to the first size. Power savings associated with the precharge circuit on the order of (Vdh/Vdl)2=36 are achieved in some embodiments.

    摘要翻译： 用于驱动与空间光调制器的微镜相关联的互补电极对的存储单元包括耦合到提供源极电压的电压源的两个PMOS晶体管。 两个PMOS晶体管的特征在于第一尺寸。 存储单元还包括耦合到地的两个NMOS晶体管。 两个NMOS晶体管中的每一个耦合到两个PMOS晶体管中的一个，并且其特征在于基本上等于第一尺寸的第二尺寸。 存储单元还包括耦合到字线的两个字线晶体管，其特征在于基本上等于第一尺寸的第三尺寸。 在一些实施例中，实现了与（Vdh / Vdl）2 = 36的顺序相关联的预充电电路的功率节省。

    LOW POWER, SMALL SIZE SRAM ARCHITECTURE
    8.
    发明申请
    LOW POWER, SMALL SIZE SRAM ARCHITECTURE 有权
    低功耗，小尺寸SRAM架构

    公开(公告)号：US20090310398A1

    公开(公告)日：2009-12-17

    申请号：US12137362

    申请日：2008-06-11

    申请人： Thu Nguyen

    发明人： Thu Nguyen

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/08

    CPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413

    摘要： A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors coupled to ground. Each of the two NMOS transistors are coupled to one of the two PMOS transistors and are characterized by a second size substantially equal to the first size. The memory cell further includes two word line transistors coupled to a word line and characterized by a third size substantially equal to the first size. Power savings associated with the precharge circuit on the order of (Vdh/Vdl)2=36 are achieved in some embodiments.

    摘要翻译： 用于驱动与空间光调制器的微镜相关联的互补电极对的存储单元包括耦合到提供源极电压的电压源的两个PMOS晶体管。 两个PMOS晶体管的特征在于第一尺寸。 存储单元还包括耦合到地的两个NMOS晶体管。 两个NMOS晶体管中的每一个耦合到两个PMOS晶体管中的一个，并且其特征在于基本上等于第一尺寸的第二尺寸。 存储单元还包括耦合到字线的两个字线晶体管，其特征在于基本上等于第一尺寸的第三尺寸。 在一些实施例中，实现了与（Vdh / Vdl）2 = 36的顺序相关联的预充电电路的功率节省。

    Increased seed size and seed number through transgenic over expression of revoluta protein during early embryo development
    9.
    发明申请
    Increased seed size and seed number through transgenic over expression of revoluta protein during early embryo development 失效
    通过在早期胚胎发育过程中通过转基因过度表达rotuta蛋白来增加种子大小和种子数量

    公开(公告)号：US20080263727A1

    公开(公告)日：2008-10-23

    申请号：US11611832

    申请日：2006-12-15

    申请人： Jay DeRocher ,  Thu Nguyen

    发明人： Jay DeRocher ,  Thu Nguyen

    IPC分类号： A01H1/00 ,  C12N15/63 ,  A01H5/00 ,  C12N5/10

    CPC分类号： C12N15/8234 ,  C12N15/8261 ,  Y02A40/146

    摘要： The present invention provides methods and compositions for increasing the seed size and/or seed number in plants. In particular, the methods and compositions provide for the over expression of a plant growth and/or development related or associated gene during embryo development. Transgenic plants transformed with genetic constructs having the plant growth and/or development associated gene under the control of an early phase-specific embryo promoter provides mature plants in the field that produce larger and/or more seeds. Methods for selection growth and development associated genes that provide transgenic plants with a higher yield phenotype are also provided.

    摘要翻译： 本发明提供用于增加植物中种子大小和/或种子数量的方法和组合物。 特别地，所述方法和组合物在胚胎发育期间提供植物生长和/或发育相关或相关基因的过度表达。 用具有早期阶段特异性胚胎启动子控制下的植物生长和/或发育相关基因的遗传构建体转化的转基因植物提供了在该领域中产生更大和/或更多种子的成熟植物。 还提供了提供具有较高产量表型的转基因植物的选择生长和发育相关基因的方法。

    Advanced food and or drink organization and or handling system
    10.
    发明授权
    Advanced food and or drink organization and or handling system 有权
    先进的食品和/或饮料组织和/或处理系统

    公开(公告)号：US07292146B1

    公开(公告)日：2007-11-06

    申请号：US11422282

    申请日：2006-06-05

    申请人： Thu Nguyen

    发明人： Thu Nguyen

    IPC分类号： G08B13/14

    CPC分类号： F25D29/00 ,  F25D2400/361 ,  F25D2500/06 ,  G06Q20/203

    摘要： An advanced food and/or drink organization and/or handling system that greatly facilitates food management and handling to help streamline household operations as relate to foods and related functions and events.

    摘要翻译： 一个先进的食品和/或饮料组织和/或处理系统，极大地促进了食品管理和处理，以帮助简化与食品和相关功能和事件相关的家庭操作。