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1.发明授权Graphene-containing semiconductor structures and devices on a silicon carbide substrate having a defined miscut angle 失效含有石墨烯的半导体结构和在具有限定的杂散角的碳化硅衬底上的器件公开(公告)号：US08476617B2
公开(公告)日：2013-07-02
申请号：US13030834
申请日：2011-02-18
申请人： Christos D. Dimitrakopoulos , Alfred Grill , Timothy J. McArdle , John A. Ott , Robert L. Wisnierff
发明人： Christos D. Dimitrakopoulos , Alfred Grill , Timothy J. McArdle , John A. Ott , Robert L. Wisnierff
CPC分类号： H01L21/02527 , H01L21/02378 , H01L21/02433 , H01L21/02612 , H01L21/02656 , H01L29/045 , H01L29/1606 , H01L29/1608 , H01L29/165 , H01L29/66045 , H01L29/66431 , H01L29/7781
摘要： A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.
摘要翻译： 提供具有高霍尔迁移率的半导体结构，其包括具有0.1°或更小的误差角的SiC衬底和位于SiC衬底的上表面上的石墨烯层。 此外，提供了包括具有0.1°或更小的误差角的SiC衬底和位于SiC衬底顶部的至少一个含石墨烯的半导体器件的半导体器件。 所述至少一个含石墨烯的半导体器件包括覆盖并与SiC衬底的上表面接触的石墨烯层。
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公开(公告)号：US08877340B2
公开(公告)日：2014-11-04
申请号：US12844029
申请日：2010-07-27
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
IPC分类号： B32B9/00
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.
摘要翻译： 在具有非六边形对称性的结晶表面上形成石墨烯层。 晶体表面可以是单晶半导体碳化物层的表面。 单晶半导体碳化物层的非六边形对称表面在超高真空环境中在升高的温度下退火以形成石墨烯层。 在退火过程中，单晶半导体碳化物层的非六边形表面上的半导体原子对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除，半导体 - 碳合金层表面上的碳浓度增加。 尽管半导体 - 碳合金层的表面具有非六边形对称性，但剩余的碳原子可以聚结形成具有六边形对称性的石墨烯层。
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公开(公告)号：US20120028052A1
公开(公告)日：2012-02-02
申请号：US12844029
申请日：2010-07-27
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.
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4.发明申请SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP 有权半导体芯片与基于图形的设备在芯片的互连结构中公开(公告)号：US20120205626A1
公开(公告)日：2012-08-16
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译： 半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。 该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。 所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。 所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。 第二电介质材料包括其中包含的至少一个第二导电区域，并且至少一个第二导电区域与至少一个含石墨烯的半导体器件的导电元件接触。
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5.发明授权Semiconductor chip with graphene based devices in an interconnect structure of the chip 有权半导体芯片采用基于石墨烯的器件，在芯片的互连结构中公开(公告)号：US08440999B2
公开(公告)日：2013-05-14
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
IPC分类号： H01L29/78
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译： 半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。 该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。 所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。 所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。 第二电介质材料包括其中包含的至少一个第二导电区域，并且所述至少一个第二导电区域与所述至少一个含石墨烯的半导体器件的导电元件接触。
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公开(公告)号：US20120319078A1
公开(公告)日：2012-12-20
申请号：US13596152
申请日：2012-08-28
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.
摘要翻译： 在具有非六边形对称性的结晶表面上形成石墨烯层。 晶体表面可以是单晶半导体碳化物层的表面。 单晶半导体碳化物层的非六边形对称表面在超高真空环境中在升高的温度下退火以形成石墨烯层。 在退火过程中，单晶半导体碳化物层的非六边形表面上的半导体原子对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除，半导体 - 碳合金层表面上的碳浓度增加。 尽管半导体 - 碳合金层的表面具有非六边形对称性，但剩余的碳原子可以聚结形成具有六边形对称性的石墨烯层。
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7.发明申请GRAPHENE-CONTAINING SEMICONDUCTOR STRUCTURES AND DEVICES ON A SILICON CARBIDE SUBSTRATE HAVING A DEFINED MISCUT ANGLE 失效在具有定义的MISCUT角度的碳化硅衬底上的含石墨的半导体结构和器件公开(公告)号：US20120211723A1
公开(公告)日：2012-08-23
申请号：US13030834
申请日：2011-02-18
申请人： Christos D. Dimitrakopoulos , Alred Grill , Timothy J. McArdle , John A. Ott , Robert L. Wisnierff
发明人： Christos D. Dimitrakopoulos , Alred Grill , Timothy J. McArdle , John A. Ott , Robert L. Wisnierff
CPC分类号： H01L21/02527 , H01L21/02378 , H01L21/02433 , H01L21/02612 , H01L21/02656 , H01L29/045 , H01L29/1606 , H01L29/1608 , H01L29/165 , H01L29/66045 , H01L29/66431 , H01L29/7781
摘要： A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.
摘要翻译： 提供具有高霍尔迁移率的半导体结构，其包括具有0.1°或更小的误差角的SiC衬底和位于SiC衬底的上表面上的石墨烯层。 此外，提供了包括具有0.1°或更小的误差角的SiC衬底和位于SiC衬底顶部的至少一个含石墨烯的半导体器件的半导体器件。 所述至少一个含石墨烯的半导体器件包括覆盖并与SiC衬底的上表面接触的石墨烯层。
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公开(公告)号：US08541769B2
公开(公告)日：2013-09-24
申请号：US12942490
申请日：2010-11-09
申请人： Jack O. Chu , Christos D. Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Robert L. Wisnieff
发明人： Jack O. Chu , Christos D. Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Robert L. Wisnieff
IPC分类号： H01L29/12
CPC分类号： H01L21/02447 , H01L21/02378 , H01L21/0242 , H01L21/02527 , H01L21/02612 , H01L21/0262 , H01L21/02656 , H01L29/1606 , H01L29/267
摘要： A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.
摘要翻译： 单晶碳化硅层可以在单晶蓝宝石衬底上生长。 随后，在超高真空环境中的高温退火期间，可以通过转换单晶硅层的表面层来形成石墨烯层。 或者，石墨烯层可以沉积在单晶碳化硅层的暴露表面上。 石墨烯层也可以直接形成在蓝宝石衬底的表面上或直接在碳化硅衬底的表面上形成。 另外，也可以在半导体基板上的碳化硅层上形成石墨烯层。 直径为6英寸或更大的蓝宝石衬底和半导体衬底的商业可用性允许在商业可扩展的衬底上形成石墨烯层，用于使用石墨烯层的器件的低成本制造。
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9.发明授权Semiconductor structure and circuit including ordered arrangement of graphene nanoribbons, and methods of forming same 有权包括石墨烯纳米带的有序排列的半导体结构和电路及其形成方法公开(公告)号：US08354296B2
公开(公告)日：2013-01-15
申请号：US13009048
申请日：2011-01-19
IPC分类号： H01L51/40
CPC分类号： H01L51/0558 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/3081 , H01L21/7624 , H01L27/088 , H01L29/0673 , H01L29/1606 , H01L29/66439 , H01L29/775 , H01L29/7781
摘要： A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.
摘要翻译： 使用确定性组装的并行纳米线组作为蚀刻掩模来提供包括位于半导体衬底的表面上的平行石墨烯纳米带的有序阵列的半导体结构。 使用电场辅助组装过程，在图案化的石墨烯层中跨越存在的间隙形成确定性组装的平行纳米线组。 可以在平行石墨烯纳米带的有序阵列上形成诸如场效应晶体管的半导体器件。
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10.发明申请SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME 有权包含石墨烯纳米粒子的顺序排列的半导体结构和电路及其形成方法公开(公告)号：US20120181507A1
公开(公告)日：2012-07-19
申请号：US13009048
申请日：2011-01-19
CPC分类号： H01L51/0558 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/3081 , H01L21/7624 , H01L27/088 , H01L29/0673 , H01L29/1606 , H01L29/66439 , H01L29/775 , H01L29/7781
摘要： A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.
摘要翻译： 使用确定性组装的并行纳米线组作为蚀刻掩模来提供包括位于半导体衬底的表面上的平行石墨烯纳米带的有序阵列的半导体结构。 使用电场辅助组装过程，在图案化的石墨烯层中跨越存在的间隙形成确定性组装的平行纳米线组。 可以在平行石墨烯纳米带的有序阵列上形成诸如场效应晶体管的半导体器件。
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