利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.014 秒)

    Method and apparatus for configuring access times of memory devices
    4.
    发明授权
    Method and apparatus for configuring access times of memory devices 失效
    用于配置存储设备的访问时间的方法和装置

    公开(公告)号：US06842864B1

    公开(公告)日：2005-01-11

    申请号：US09685014

    申请日：2000-10-05

    申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/00

    CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02D10/151

    摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

    摘要翻译： 提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。 确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。 随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。 然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。 在确定每个DRAM器件的响应时间并使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合 总线等于最长响应时间。 通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

    Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
    8.
    发明授权
    Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain 失效
    通过调整读取域来初始化动态随机存取存储器（DRAM）设备的方法和装置

    公开(公告)号：US6154821A

    公开(公告)日：2000-11-28

    申请号：US38358

    申请日：1998-03-10

    申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/00

    CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C7/20 ,  G11C8/12 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02B60/1235

    摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

    摘要翻译： 提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。 确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。 随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。 然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。 在确定每个DRAM器件的响应时间并且使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合 总线等于最长响应时间。 通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。