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    Method and apparatus for configuring access times of memory devices
    6.
    发明授权
    Method and apparatus for configuring access times of memory devices 失效
    用于配置存储设备的访问时间的方法和装置

    公开(公告)号：US06842864B1

    公开(公告)日：2005-01-11

    申请号：US09685014

    申请日：2000-10-05

    申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/00

    CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02D10/151

    摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

    摘要翻译： 提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。 确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。 随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。 然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。 在确定每个DRAM器件的响应时间并使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合 总线等于最长响应时间。 通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

    Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
    8.
    发明授权
    Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain 失效
    通过调整读取域来初始化动态随机存取存储器（DRAM）设备的方法和装置

    公开(公告)号：US6154821A

    公开(公告)日：2000-11-28

    申请号：US38358

    申请日：1998-03-10

    申请人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    发明人： Richard M. Barth ,  Ely K. Tsern ,  Craig E. Hampel ,  Frederick A. Ware ,  Todd W. Bystrom ,  Bradley A. May ,  Paul G. Davis

    IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G06F13/00

    CPC分类号： G11C7/1072 ,  G06F1/3225 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4239 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C7/20 ,  G11C8/12 ,  G11C2207/2227 ,  G11C2207/2254 ,  Y02B60/1235

    摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.

    摘要翻译： 提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。 确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。 随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。 然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。 在确定每个DRAM器件的响应时间并且使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合 总线等于最长响应时间。 通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

    Rambus DRAM (RDRAM) apparatus and method for performing refresh operations
    9.
    发明授权
    Rambus DRAM (RDRAM) apparatus and method for performing refresh operations 失效
    用于执行刷新操作的DRAM装置和方法

    公开(公告)号：US06310814B1

    公开(公告)日：2001-10-30

    申请号：US09637892

    申请日：2000-08-08

    申请人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

    发明人： Craig E. Hampel ,  Richard M. Barth ,  Paul G. Davis ,  Bradley A. May ,  Ramprasad Satagopan ,  Frederick A. Ware

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： An apparatus and method for concurrently refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) component that includes a plurality of banks of memory cells organized in rows. A command interface in the DRAM component receives activate requests and precharge requests. A row register in the DRAM component indicates a row in the DRAM component. Logic in the DRAM component activates the row indicated by the row register in response to an activate request and precharges the row in response to a precharge request, the row being in a bank indicated by the activate request and by the precharge request.

    摘要翻译： 一种用于在动态随机存取存储器（DRAM）组件中同时刷新第一和第二行存储器单元的装置和方法，所述动态随机存取存储器（DRAM）组件包括以行为单位组织的多组存储器单元。 DRAM组件中的命令接口接收激活请求和预充电请求。 DRAM组件中的行寄存器表示DRAM组件中的一行。 DRAM组件中的逻辑响应于激活请求而激活由行寄存器指示的行，并且响应于预充电请求预先充电该行，该行位于由激活请求指示的存储体中以及通过预充电请求。

    Apparatus and method for decoding four states with one pin
    10.
    发明授权
    Apparatus and method for decoding four states with one pin 失效
    用一个引脚解码四个状态的装置和方法

    公开(公告)号：US5023483A

    公开(公告)日：1991-06-11

    申请号：US372070

    申请日：1989-06-27

    申请人： Bradley A. May

    发明人： Bradley A. May

    IPC分类号： G06F1/22 ,  H03K19/173

    CPC分类号： H03K19/1732 ,  G06F1/22

    摘要： According to one aspect of the invention, a novel control circuit is coupled to a pin at a circuit node. The circuit node has a particular default condition of one of two logic states. The control circuit stores the default value and subsequently attempts to drive an alternate logic state onto the pin. The circuit then reads the logic state at the pin to determine if there has been a change of logic state registered. If a change has been registered, then the existence of a third condition or fourth condition is indicated, depending upon the default logic state.

    摘要翻译： 根据本发明的一个方面，一种新颖的控制电路耦合到电路节点处的引脚。 电路节点具有两种逻辑状态之一的特定默认状态。 控制电路存储默认值，并随后尝试将引脚上的备用逻辑状态驱动。 然后，电路读取引脚上的逻辑状态，以确定是否已经注册了逻辑状态的改变。 如果已经注册了更改，则根据默认逻辑状态指示存在第三条件或第四条件。