公开(公告)号：US07671417B2

公开(公告)日：2010-03-02

申请号：US11840559

申请日：2007-08-17

申请人： Eiji Yoshida ,  Tetsu Tanaka ,  Toshihiko Miyashita

发明人： Eiji Yoshida ,  Tetsu Tanaka ,  Toshihiko Miyashita

IPC分类号： H01L29/72

CPC分类号： H01L21/845 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7841 ,  H01L29/785

摘要： A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front gate region formed on a gate insulating film formed on one of side surfaces of the semiconductor region such that the source region and the drain region are separated from each other by the front gate region, and a back gate region formed on a gate insulating film formed on an opposite side surface of the semiconductor region such that the source region and the drain region are separated from each other by the back gate region. Each memory cell shares the back gate region with a memory cell adjacent in a row direction.

摘要翻译： 存储单元阵列包括形成在支撑绝缘基板上的隔离半导体区域，形成在各个半导体区域中的存储单元，以及形成为使得存储单元绝缘的绝缘区域。 形成在半导体区域中的每个存储单元包括源极区域，漏极区域，形成在形成在半导体区域的一个侧表面上的栅极绝缘膜上的前栅极区域，使得源极区域和漏极区域与每个 以及形成在栅极绝缘膜上的背栅极区域，该栅极绝缘膜形成在半导体区域的相对侧表面上，使得源极区域和漏极区域由背栅极区域彼此分离。 每个存储单元与在行方向上相邻的存储单元共享背栅区。

公开(公告)号：US20090128469A1

公开(公告)日：2009-05-21

申请号：US12084261

申请日：2006-06-06

申请人： Toshihiko Miyashita

发明人： Toshihiko Miyashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/20 ,  G09G2320/0223 ,  G09G2330/04

摘要： The present invention relates to a display device and an electronic device provided with same.An object of the present invention is to improve an electrostatic withstand voltage of the display device, thereby suppressing breakage of an electric circuit formed in a panel due to static electricity.An intra-panel protective circuit (120) is provided between an input/output terminal (300) of a liquid crystal panel (10) and an intra-panel electric circuit (110), and, an intra-LSI protective circuit (220) is provided between the input/output terminal (300) of the liquid crystal panel (10) and a liquid crystal controller (210) in an LSI (200). A signal line connecting the input/output terminal (300) with the intra-panel electric circuit (110) and a signal line connecting the input/output terminal (300) with the liquid crystal controller (210) are connected with two diodes, respectively. On of the diodes is connected with signal lines (48, 28) to which a power supply voltage at a high potential is supplied, and the other one of the diodes is connected with signal lines (49, 29) to which a power supply voltage at a low potential is supplied.

摘要翻译： 本发明涉及一种显示装置及具备该显示装置的电子装置。 本发明的目的是提高显示装置的静电耐受电压，从而抑制由于静电而在面板上形成的电路的破坏。 在液晶面板（10）的输入输出端子（300）和面板内电路（110）之间设置面板内保护电路（120），LSI内保护电路（220） 设置在液晶面板（10）的输入输出端子（300）和LSI（200）中的液晶控制器（210）之间。 将输入输出端子（300）与面板内电路（110）连接的信号线和将输入输出端子（300）与液晶控制器（210）连接的信号线分别与两个二极管连接 。 二极管的导通与提供高电位的电源电压的信号线（48,28）连接，另一个二极管与信号线（49,29）连接，在该信号线（49,29）上连接有电源电压 提供低电位。

公开(公告)号：US20080231641A1

公开(公告)日：2008-09-25

申请号：US11991309

申请日：2006-05-25

申请人： Toshihiko Miyashita

发明人： Toshihiko Miyashita

IPC分类号： G09G3/20

CPC分类号： G09G3/3655 ,  G02F1/136259 ,  G09G2300/0876 ,  G09G2330/026 ,  G09G2330/10

摘要： In one embodiment of the present application, a display is disclosed in which any defective pixel is rendered less noticeable even if a full-screen white display or suchlike is effected. In a normally-white liquid crystal display device, which transitions after power activation from non-display state through display starting state, where a full-screen blank white display is effected, to normal display state, an auxiliary electrode driver portion controls an auxiliary capacitance line voltage Vcs to be applied to auxiliary capacitance lines in accordance with the state of the liquid crystal display device in the following manner. Specifically, during the display starting state, the voltage difference between the auxiliary capacitance line voltage Vcs and a counter voltage Vcom is set at 0, such that any defective pixel is displayed in white, whereas during the normal display state, a predetermined voltage difference ΔVc is caused between the auxiliary capacitance line voltage VCS and the counter voltage Vcom, such that any defective pixel is displayed in black. The present invention is suitable for active-matrix liquid crystal display devices.

摘要翻译： 在本申请的一个实施例中，公开了一种显示器，其中即使实现全屏白色显示器等，任何缺陷像素都变得不显着。 在正常白色液晶显示装置中，辅助电极驱动部分从辅助电极驱动器部分控制辅助电极驱动部分，其中，该常规白色液晶显示装置在从非显示状态到实施全屏空白白色显示的显示开始状态的电力激活之后转换到正常显示状态， 根据液晶显示装置的状态按照以下的方式施加到辅助电容线的线电压V Cs / S。 具体地，在显示开始状态期间，辅助电容线电压V SUB和电压V SUB之间的电压差设定为0，使得任何缺陷像素为 显示为白色，而在正常显示状态期间，在辅助电容线电压VCS和反电压V SUB之间产生预定的电压差DeltaV C，使得任何 缺陷像素以黑色显示。 本发明适用于有源矩阵液晶显示装置。

公开(公告)号：US20080142855A1

公开(公告)日：2008-06-19

申请号：US11958615

申请日：2007-12-18

申请人： Keiji IKEDA ,  Toshihiko MIYASHITA

发明人： Keiji IKEDA ,  Toshihiko MIYASHITA

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7849

摘要： A MOS transistor includes a silicon substrate, a gate insulating film disposed on the silicon substrate, a gate electrode disposed on the gate insulating film, source/drain regions disposed at both sides of the gate electrode, and a stress-generating region containing a stress-generating substance. The stress-generating region is disposed within the silicon substrate away from a surface of the silicon substrate, between the source/drain regions, and under the gate electrode.

摘要翻译： MOS晶体管包括硅衬底，设置在硅衬底上的栅极绝缘膜，设置在栅极绝缘膜上的栅电极，设置在栅电极两侧的源极/漏极区域和包含应力的应力产生区域 生成物质。 应力产生区域设置在硅衬底内远离硅衬底的表面，源极/漏极区域之间以及栅电极下方。

公开(公告)号：US20060220114A1

公开(公告)日：2006-10-05

申请号：US11192424

申请日：2005-07-29

申请人： Toshihiko Miyashita ,  Kunihiro Suzuki

发明人： Toshihiko Miyashita ,  Kunihiro Suzuki

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/28238 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/6659

摘要： An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor film, and impurities to become the source/drain are introduced in this state. Then the impurities are activated, and the amorphized portion is recrystallized, by low temperature solid-phase epitaxial regrowth. With the processing temperature required for the low temperature solid-phase epitaxial regrowth being within a range of 450° C.-650° C., thermal diffusion of the impurities into the semiconductor film is suppressed, thereby maintaining the initial steep step-profile.

摘要翻译： 可以容易且可靠地实现通道区域中的理想阶梯轮廓，从而一起实现短路效应的抑制和防止迁移率降低。 硅衬底从半导体膜非晶化到预定深度，并且在该状态下引入成为源极/漏极的杂质。 然后杂质被活化，非晶化部分通过低温固相外延再生长再结晶。 由于低温固相外延再生长所需的处理温度在450℃-650℃的范围内，因此能够抑制杂质向半导体膜的热扩散，从而保持初始陡峭的阶梯型。

公开(公告)号：US09159286B2

公开(公告)日：2015-10-13

申请号：US13515178

申请日：2010-10-28

申请人： Hiromi Enomoto ,  Shinsuke Yokonuma ,  Yoji Inui ,  Toshihiko Miyashita ,  Hiroyuki Kitamura

发明人： Hiromi Enomoto ,  Shinsuke Yokonuma ,  Yoji Inui ,  Toshihiko Miyashita ,  Hiroyuki Kitamura

IPC分类号： G09G3/36

CPC分类号： G09G3/3677

摘要： The present invention includes, in addition to transistors each (Mm,n) provided at the intersection of a gate bus line (GLn) with a data bus line (DLm): block potential applying transistors (DMn) connected to respective ends of gate bus lines (GLn) which ends are not connected to a gate driver (11); a potential supply line (VLL) connected to the gate bus lines (GLn) via the block potential applying transistors (DMn); and a blocking signal supplying section (131) for, immediately after the gate driver (11) supplies a first conduction signal for bringing the transistors (Mm,n) into conduction, supplying to the block potential applying transistors (DMn), a second conduction signal for bringing the block potential applying transistors (DMn) into conduction.

摘要翻译： 除了设置在栅极总线（GLn）与数据总线（DLm）的交点处的每个（Mm，n）之外，本发明还包括：连接到栅极总线的各端的块电位施加晶体管（DMn） 末端的线（GLn）不连接到栅极驱动器（11）; 通过块电位施加晶体管（DMn）连接到栅极总线（GLn）的电位供应线（VLL）; 和闭锁信号提供部分（131），用于在栅极驱动器（11）提供用于使晶体管（Mm，n）导通的第一导通信号之后，向块电位施加晶体管（DMn）提供第二导通 用于使块电位施加晶体管（DMn）导通的信号。

公开(公告)号：US08390552B2

公开(公告)日：2013-03-05

申请号：US11991309

申请日：2006-05-25

申请人： Toshihiko Miyashita

发明人： Toshihiko Miyashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3655 ,  G02F1/136259 ,  G09G2300/0876 ,  G09G2330/026 ,  G09G2330/10

摘要： In one embodiment of the present application, a display is disclosed in which any defective pixel is rendered less noticeable even if a full-screen white display or suchlike is effected. In a normally-white liquid crystal display device, which transitions after power activation from non-display state through display starting state, where a full-screen blank white display is effected, to normal display state, an auxiliary electrode driver portion controls an auxiliary capacitance line voltage Vcs to be applied to auxiliary capacitance lines in accordance with the state of the liquid crystal display device in the following manner. Specifically, during the display starting state, the voltage difference between the auxiliary capacitance line voltage Vcs and a counter voltage Vcom is set at 0, such that any defective pixel is displayed in white, whereas during the normal display state, a predetermined voltage difference ΔVc is caused between the auxiliary capacitance line voltage Vcs and the counter voltage Vcom, such that any defective pixel is displayed in black. The present invention is suitable for active-matrix liquid crystal display devices.

摘要翻译： 在本申请的一个实施例中，公开了一种显示器，其中即使实现全屏白色显示器等，任何缺陷像素都变得不显着。 在正常白色液晶显示装置中，辅助电极驱动部分从辅助电极驱动器部分控制辅助电极驱动部分，其中，该常规白色液晶显示装置在从非显示状态到实施全屏空白白色显示的显示开始状态的电力激活之后转换到正常显示状态， 线电压Vcs根据液晶显示装置的状态以下列方式施加到辅助电容线。 具体地说，在显示开始状态期间，将辅助电容线电压Vcs与反电压Vcom之间的电压差设定为0，使得任何缺陷像素以白色显示，而在正常显示状态期间，预定电压差Dgr ;在辅助电容线电压Vcs和反电压Vcom之间产生Vc，使得任何有缺陷的像素以黑色显示。 本发明适用于有源矩阵液晶显示装置。

公开(公告)号：US20100075476A1

公开(公告)日：2010-03-25

申请号：US12544810

申请日：2009-08-20

申请人： Toshihiko Miyashita

发明人： Toshihiko Miyashita

IPC分类号： H01L21/8238 ,  H01L21/77 ,  H01L21/265

CPC分类号： H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.

摘要翻译： 一种制造半导体器件的方法，包括形成第一和第二栅极图案，分别在第一和第二栅极图案的侧壁上形成第一和第二侧壁间隔物，将第一杂质注入到半导体衬底中，在第一和第二栅极图案上形成第三侧壁间隔物 侧壁间隔件和第二侧壁间隔件，使得第三侧壁间隔件与第一和第二栅极图案之间的第四侧壁间隔物接触，将第二杂质注入到半导体衬底中，并且移除第三侧壁间隔物 和第四侧壁间隔件。

公开(公告)号：US20100025744A1

公开(公告)日：2010-02-04

申请号：US12561841

申请日：2009-09-17

申请人： Toshihiko Miyashita ,  Keiji Ikeda

发明人： Toshihiko Miyashita ,  Keiji Ikeda

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer configured to apply stress to the channel region, the strain generation layer being configured to apply greater stress in absolute value to the source edge of the channel region than to the drain edge of the channel region.

摘要翻译： 半导体器件包括在半导体衬底上的栅极电极，设置在栅电极下方的半导体衬底中的沟道区域和被配置为向沟道区域施加应力的应变生成层，应变发生层被配置为在 与通道区域的漏极边缘相比，沟道区源极边缘的绝对值。

公开(公告)号：US07312500B2

公开(公告)日：2007-12-25

申请号：US11785465

申请日：2007-04-18

申请人： Toshihiko Miyashita ,  Kunihiro Suzuki

发明人： Toshihiko Miyashita ,  Kunihiro Suzuki

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/28238 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/6659

摘要： An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor film, and impurities to become the source/drain are introduced in this state. Then the impurities are activated, and the amorphized portion is recrystallized, by low temperature solid-phase epitaxial regrowth. With the processing temperature required for the low temperature solid-phase epitaxial regrowth being within a range of 450° C.-650° C., thermal diffusion of the impurities into the semiconductor film is suppressed, thereby maintaining the initial steep step-profile.