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公开(公告)号：US08497547B2
公开(公告)日：2013-07-30
申请号：US13591035
申请日：2012-08-21
申请人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
发明人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
IPC分类号： H01L27/115
CPC分类号： H01L29/7885 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328
摘要： Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
摘要翻译： 提供了一种在半导体衬底上具有彼此相邻并构成非易失性存储器的控制栅电极和存储栅电极的半导体器件。 存储栅电极的高度低于控制栅电极的高度。 在控制栅电极的上表面上形成金属硅化物膜，但不形成在存储栅电极的上表面上。 存储栅电极在其上表面上具有由氧化硅制成的侧壁绝缘膜。 该侧壁绝缘膜以与用于在存储栅电极和控制栅电极的侧壁上形成各个侧壁绝缘膜的步骤相同的步骤形成。 本发明使得可以提高具有非易失性存储器的半导体器件的生产率和性能。
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公开(公告)号：US20120306051A1
公开(公告)日：2012-12-06
申请号：US13587008
申请日：2012-08-16
IPC分类号： H01L27/08
CPC分类号： H01L28/60 , H01L27/0629 , H01L27/0805 , H01L27/105 , H01L27/10805 , H01L27/11526 , H01L27/11531 , H01L27/11573 , H01L28/40
摘要： In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
摘要翻译： 关于包括电容器元件的半导体器件，提供了一种能够提高电容器元件的可靠性的技术。 电容器元件形成在半导体衬底上形成的元件隔离区域中。 电容器元件包括通过电容器绝缘膜形成在下电极上的下电极和上电极。 基本上，下电极和上电极由形成在多晶硅膜的表面上的多晶硅膜和硅化钴膜形成。 形成在上电极上的钴硅化物膜的端部与上电极的端部间隔开一定距离。 此外，形成在下电极上的钴硅化物膜的端部与上电极和下电极之间的边界间隔一定距离。
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公开(公告)号：US08278169B2
公开(公告)日：2012-10-02
申请号：US12885086
申请日：2010-09-17
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.
摘要翻译： 本发明提供一种能够在提高非易失性存储器的可靠性的同时减少由非易失性存储器占据的面积的技术。 在半导体器件中，代码闪存单元的结构与数据闪存单元的结构不同。 更具体地，在代码闪速存储单元中，仅在控制栅电极的一侧的侧面上形成存储栅电极，以提高读取速度。 另一方面，在数据闪存单元中，在控制栅电极的两侧的侧面上形成存储栅电极。 通过使用多值存储单元而不是二进制存储单元，所得到的数据闪存单元可以提高可靠性，同时防止保留性能的劣化并减小其面积。
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公开(公告)号：US08269266B2
公开(公告)日：2012-09-18
申请号：US12825147
申请日：2010-06-28
申请人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
发明人： Koichi Toba , Yasushi Ishii , Yoshiyuki Kawashima , Satoru Machida , Munekatsu Nakagawa , Takashi Hashimoto
IPC分类号： H01L27/115
CPC分类号： H01L29/7885 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328
摘要： Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
摘要翻译： 提供了一种在半导体衬底上具有彼此相邻并构成非易失性存储器的控制栅电极和存储栅电极的半导体器件。 存储栅电极的高度低于控制栅电极的高度。 在控制栅电极的上表面上形成金属硅化物膜，但不形成在存储栅电极的上表面上。 存储栅电极在其上表面上具有由氧化硅制成的侧壁绝缘膜。 该侧壁绝缘膜以与用于在存储栅电极和控制栅电极的侧壁上形成各个侧壁绝缘膜的步骤相同的步骤形成。 本发明使得可以提高具有非易失性存储器的半导体器件的生产率和性能。
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公开(公告)号：US20120132978A1
公开(公告)日：2012-05-31
申请号：US13302184
申请日：2011-11-22
申请人： Koichi TOBA , Yasushi Ishi , Hiraku Chakihara , Kota Funayama , Yoshiyuki Kawashima , Takashi Hashimoto
发明人： Koichi TOBA , Yasushi Ishi , Hiraku Chakihara , Kota Funayama , Yoshiyuki Kawashima , Takashi Hashimoto
IPC分类号： H01L29/788 , H01L21/28 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/11573 , H01L29/42344 , H01L29/792
摘要： A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
摘要翻译： 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。
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公开(公告)号：US07687850B2
公开(公告)日：2010-03-30
申请号：US11785103
申请日：2007-04-13
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L29/42344
摘要： This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate, adjacent to the upper oxide film. A second cavity is disposed, in a position between the nitride film and a substrate and below an end portion of the memory gate, adjacent to the bottom oxide film. These cavities are closed with sidewall spacers formed over the substrate along the sidewalls of the memory gate.
摘要翻译： 本发明是提高具有ONO膜的非易失性存储单元的数据保持性能。 在作为电荷存储膜的氮化物膜和存储器栅极之间的位置以及存储栅极的端部的下方，与上部氧化物膜相邻的位置设置有第一空腔。 在氮化物膜和衬底之间的位置以及与存储器栅极的端部下方邻近底部氧化膜的第二腔体。 这些空腔被封闭，侧壁隔离物沿着存储器门的侧壁形成在衬底上。
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公开(公告)号：US20090050956A1
公开(公告)日：2009-02-26
申请号：US12191958
申请日：2008-08-14
申请人： TETSUYA ISHIMARU , YOSHIYUKI KAWASHIMA , YASUHIRO SHIMAMOTO , KAN YASUI , TSUYOSHI ARIGANE , TOSHIYUKI MINE
发明人： TETSUYA ISHIMARU , YOSHIYUKI KAWASHIMA , YASUHIRO SHIMAMOTO , KAN YASUI , TSUYOSHI ARIGANE , TOSHIYUKI MINE
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： In a memory cell including an nMIS for memory formed on the sides of an nMIS for select and an nMIS for select via dielectric films and a charge storage layer, the thickness of a gate dielectric under the gate longitudinal direction end of a select gate electrode is formed thicker than that of the gate dielectric under the gate longitudinal direction center and the thickness of the lower layer dielectric film that is positioned between the select gate electrode and the charge storage layer and is nearest to a semiconductor substrate is formed 1.5 times or below of the thickness of the lower layer dielectric film positioned between the semiconductor substrate and the charge storage layer.
摘要翻译： 在包括形成在用于选择的nMIS的侧面上的存储器的nMIS和通过电介质膜和电荷存储层进行选择的nMIS的存储单元中，选择栅电极的栅极纵向端的栅极电介质的厚度为 在栅极纵向中心处形成得比栅极电介质厚，并且位于选择栅电极和电荷存储层之间并且最靠近半导体衬底的下层电介质膜的厚度形成为1.5倍以下 位于半导体衬底和电荷存储层之间的下层电介质膜的厚度。
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公开(公告)号：US20090001449A1
公开(公告)日：2009-01-01
申请号：US12132609
申请日：2008-06-03
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/42344 , H01L29/792
摘要： The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.
摘要翻译： 本发明提供一种能够在提高非易失性存储器的可靠性的同时减少由非易失性存储器占据的面积的技术。 在半导体器件中，代码闪存单元的结构与数据闪存单元的结构不同。 更具体地，在代码闪速存储单元中，仅在控制栅电极的一侧的侧面上形成存储栅电极，以提高读取速度。 另一方面，在数据闪存单元中，在控制栅电极的两侧的侧面上形成存储栅电极。 通过使用多值存储单元而不是二进制存储单元，所得到的数据闪存单元可以提高可靠性，同时防止保留性能的劣化并减小其面积。
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公开(公告)号：US20080151629A1
公开(公告)日：2008-06-26
申请号：US12020393
申请日：2008-01-25
申请人： Fumitoshi ITO , Yoshiyuki Kawashima , Takeshi Sakai , Yasushi Ishii , Yasuhiro Kanamaru , Takashi Hashimoto , Makoto Mizuno , Kousuke Okuyama , Yukiko Manabe
发明人： Fumitoshi ITO , Yoshiyuki Kawashima , Takeshi Sakai , Yasushi Ishii , Yasuhiro Kanamaru , Takashi Hashimoto , Makoto Mizuno , Kousuke Okuyama , Yukiko Manabe
IPC分类号： G11C11/40 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , H01L21/28282 , H01L27/115 , H01L29/42344 , H01L29/66833 , H01L29/792
摘要： The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
摘要翻译： 改善了具有非易失性存储元件的半导体器件的积分度和重写次数。 与第一MONOS非易失性存储元件相比，具有大门宽度的第一MONOS非易失性存储元件和第二MONOS非易失性存储元件一起安装在同一衬底上，并且第一MONOS非易失性存储元件是 用于存储几乎不被重写的程序数据，并且第二MONOS非易失性存储元件用于存储频繁重写的处理数据。
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公开(公告)号：US20070278564A1
公开(公告)日：2007-12-06
申请号：US11785103
申请日：2007-04-13
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L29/42344
摘要： This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate, adjacent to the upper oxide film. A second cavity is disposed, in a position between the nitride film and a substrate and below an end portion of the memory gate, adjacent to the bottom oxide film. These cavities are closed with sidewall spacers formed over the substrate along the sidewalls of the memory gate.
摘要翻译： 本发明是提高具有ONO膜的非易失性存储单元的数据保持性能。 在作为电荷存储膜的氮化物膜和存储器栅极之间的位置以及存储栅极的端部的下方，与上部氧化物膜相邻的位置设置有第一空腔。 在氮化物膜和衬底之间的位置以及与存储器栅极的端部下方邻近底部氧化膜的第二腔体。 这些空腔被封闭，侧壁隔离物沿着存储器门的侧壁形成在衬底上。
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