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    Delay generator
    1.
    发明授权
    Delay generator 有权
    延迟发生器

    公开(公告)号：US08441295B2

    公开(公告)日：2013-05-14

    申请号：US13289229

    申请日：2011-11-04

    Applicant: He-Gong Wei ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo da Silva Martins

    Inventor： He-Gong Wei ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo da Silva Martins

    IPC: H03H11/06

    CPC classification number: H03K5/133 ,  H03K5/14

    Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.

    Abstract translation: 延迟发生器包括：用于提供电流的电流源; 连接到电流源的第一延迟部分，包括至少多个反相器和具有第一电容的第一电容器; 以及连接到所述电流源的第二延迟部分，包括至少多个反相器和具有第二电容的第二电容器，其中所述第一电容与所述第二电容相同，其中所述第一延迟部分产生第一延迟， 第一电容器的放电，其中第二延迟部分通过对第二电容器进行充电来产生第二延迟，并且其中由延迟发生器产生的总延迟通过第一延迟和第二延迟的相加获得。

    N-BITS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTING CIRCUIT
    5.
    发明申请
    N-BITS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTING CIRCUIT 有权
    N-bit连续逼近寄存器模拟到数字转换电路

    公开(公告)号：US20120306679A1

    公开(公告)日：2012-12-06

    申请号：US13150508

    申请日：2011-06-01

    Applicant: Yan ZHU ,  Chi-Hang CHAN ,  U-Fat CHIO ,  Sai-Weng SIN ,  Seng-Pan U ,  Rui Paulo Da Silva MARTINS ,  Franco MALOBERTI

    Inventor： Yan ZHU ,  Chi-Hang CHAN ,  U-Fat CHIO ,  Sai-Weng SIN ,  Seng-Pan U ,  Rui Paulo Da Silva MARTINS ,  Franco MALOBERTI

    IPC: H03M1/12

    CPC classification number: H03M1/002 ,  H03M1/466

    Abstract: The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

    Abstract translation: 本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络 包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压 参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。 比较器包括第一前置放大器，第二前置放大器和动态锁存器。 替代方案，比较器包括四输入前置放大器和动态锁存器。

    N-bits successive approximation register analog-to-digital converting circuit
    7.
    发明授权
    N-bits successive approximation register analog-to-digital converting circuit 有权
    N位逐次逼近寄存器模数转换电路

    公开(公告)号：US08344931B2

    公开(公告)日：2013-01-01

    申请号：US13150508

    申请日：2011-06-01

    Applicant: Yan Zhu ,  Chi-Hang Chan ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo Da Silva Martins ,  Franco Maloberti

    Inventor： Yan Zhu ,  Chi-Hang Chan ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo Da Silva Martins ,  Franco Maloberti

    IPC: H03M1/12

    CPC classification number: H03M1/002 ,  H03M1/466

    Abstract: The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

    Abstract translation: 本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络 包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压 参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。 比较器包括第一前置放大器，第二前置放大器和动态锁存器。 替代方案，比较器包括四输入前置放大器和动态锁存器。

    DELAY GENERATOR
    8.
    发明申请
    DELAY GENERATOR 有权
    延时发电机

    公开(公告)号：US20120286840A1

    公开(公告)日：2012-11-15

    申请号：US13289229

    申请日：2011-11-04

    Applicant: He-Gong Wei ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo da Silva Martins

    Inventor： He-Gong Wei ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo da Silva Martins

    IPC: H03H11/26

    CPC classification number: H03K5/133 ,  H03K5/14

    Abstract: A delay generator comprises: a current source for supplying a current; a first delay portion, connected to the current source, comprising at least a plurality of inverters and a first capacitor having a first capacitance; and a second delay portion, connected to the current source, comprising at least a plurality of inverters and a second capacitor having a second capacitance, wherein the first capacitance is the same as the second capacitance, wherein the first delay portion generates a first delay by discharging of the first capacitor, wherein the second delay portion generates a second delay by charging of the second capacitor, and wherein the total delay generated by the delay generator is obtained by summation of the first delay and the second delay.

    Abstract translation: 延迟发生器包括：用于提供电流的电流源; 连接到电流源的第一延迟部分，包括至少多个反相器和具有第一电容的第一电容器; 以及连接到所述电流源的第二延迟部分，包括至少多个反相器和具有第二电容的第二电容器，其中所述第一电容与所述第二电容相同，其中所述第一延迟部分产生第一延迟， 第一电容器的放电，其中第二延迟部分通过对第二电容器进行充电来产生第二延迟，并且其中由延迟发生器产生的总延迟通过第一延迟和第二延迟的相加获得。

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