公开(公告)号：US07786804B2

公开(公告)日：2010-08-31

申请号：US12606194

申请日：2009-10-27

申请人： Uday Dasgupta

发明人： Uday Dasgupta

IPC分类号： H03F3/26

CPC分类号： H03F3/45475 ,  H03F3/45901 ,  H03F2203/45212 ,  H03F2203/45216 ,  H03F2203/45222 ,  H03F2203/45512 ,  H03F2203/45644 ,  H03F2203/45646 ,  H03F2203/45724

摘要： A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.

摘要翻译： 驱动放大器电路包括：用于向负载提供负载电流的第一驱动器; 用于从负载中吸收负载电流的第二个驱动器; 用于驱动第一驱动器的第一运算放大器（运算放大器）; 用于驱动第二驱动器的第二运算放大器; 用于偏置第一驱动器的第一偏置电路; 用于偏置所述第二驱动器的第二偏置电路; 使能电路，用于根据控制信号启动第一偏置电路或第二偏置电路; 数字控制电路，用于监视第一驱动器和第二驱动器的电流以产生控制信号; 以及偏移均衡电路，耦合在所述第一运算放大器的内部节点和所述第二运算放大器的内部节点之间，用于调整所述第一运算放大器和所述第二运算放大器中的至少一个的DC偏移。

公开(公告)号：US07764122B1

公开(公告)日：2010-07-27

申请号：US12337955

申请日：2008-12-18

申请人： Uday Dasgupta

发明人： Uday Dasgupta

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F3/3022 ,  H03F2200/78 ,  H03F2203/45138 ,  H03F2203/45244 ,  H03F2203/45536

摘要： An amplifier circuit includes a first stage to generate a first stage output based on a signal input and a control input. A second stage in communication with the first stage output and the control input. The second stage includes a first current source driver operable in a constant current source mode or a driver mode. The first current source driver operates in either the constant current source mode or the driver mode based on the signal input and the control input.

摘要翻译： 放大器电路包括基于信号输入和控制输入产生第一级输出的第一级。 与第一阶段输出和控制输入通信的第二阶段。 第二级包括可在恒流源模式或驱动器模式下操作的第一电流源驱动器。 第一个电流源驱动器基于信号输入和控制输入在恒流源模式或驱动模式下工作。

公开(公告)号：US20090295482A1

公开(公告)日：2009-12-03

申请号：US12131138

申请日：2008-06-02

申请人： Uday Dasgupta ,  Alexander Tanzil

发明人： Uday Dasgupta ,  Alexander Tanzil

IPC分类号： H03F3/26

CPC分类号： H03F3/303 ,  H03F3/45475 ,  H03F3/72 ,  H03F2203/45648 ,  H03F2203/45674 ,  H03F2203/45711 ,  H03F2203/45724 ,  H03F2203/7206

摘要： A driving amplifier circuit includes: a first driver for souring a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) coupled to a differential input signal for driving the first driver; a second operational amplifier coupled to the differential input signal for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit, coupled to the first bias circuit and the second bias circuit, for enabling either the first bias circuit or the second bias circuit according to a control signal; and a digital control circuit, coupled to the enabling circuit, for monitoring currents of the first driver and the second driver to generate the control signal.

摘要翻译： 驱动放大器电路包括：第一驱动器，用于向负载提供负载电流; 用于从负载中吸收负载电流的第二个驱动器; 耦合到用于驱动第一驱动器的差分输入信号的第一运算放大器（运算放大器）; 耦合到用于驱动第二驱动器的差分输入信号的第二运算放大器; 用于偏置第一驱动器的第一偏置电路; 用于偏置所述第二驱动器的第二偏置电路; 耦合到第一偏置电路和第二偏置电路的使能电路，用于根据控制信号实现第一偏置电路或第二偏置电路; 以及耦合到使能电路的数字控制电路，用于监视第一驱动器和第二驱动器的电流以产生控制信号。

公开(公告)号：US07592871B1

公开(公告)日：2009-09-22

申请号：US12287964

申请日：2008-10-15

申请人： Uday Dasgupta

发明人： Uday Dasgupta

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/34 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2200/513 ,  H03F2203/45366 ,  H03F2203/45431

摘要： A differential current amplifier circuit includes a first circuit generating a first pair of output currents based on a first input current to the differential current amplifier circuit. A second circuit generates a second pair of output currents based on a second input current to the differential current amplifier circuit. A first subtraction circuit generates a first output voltage based on a difference between one of the first pair of output currents and one of the second pair of output currents. A second subtraction circuit generates a second output voltage based on a difference between the other one of the second pair of output currents and the other one of the first pair of output currents.

摘要翻译： 差分电流放大器电路包括基于对差分电流放大器电路的第一输入电流产生第一对输出电流的第一电路。 第二电路基于到差分电流放大器电路的第二输入电流产生第二对输出电流。 第一减法电路基于第一对输出电流中的一个与第二对输出电流中的一个之间的差产生第一输出电压。 第二减法电路基于第二对输出电流中的另一个与第一对输出电流中的另一个之间的差产生第二输出电压。

公开(公告)号：US07215198B1

公开(公告)日：2007-05-08

申请号：US10950201

申请日：2004-09-24

申请人： Uday Dasgupta

发明人： Uday Dasgupta

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/34 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2200/513 ,  H03F2203/45366 ,  H03F2203/45431

摘要： A fully differential current feedback amplifier suitable for using in a fully differential operational amplifier circuit is disclosed. Symmetrical low input impedance input circuits receive a differential input current and provide a set of four currents that correspond to the differential input currents. These current are input to a pair of subtraction circuits that output a first voltage signal responsive to the positive difference and a second voltage signal responsive to the negative difference. In some embodiments these signals may be further amplified. A common mode circuit is provided that averages the output voltage and feeds back current in response to the subtraction circuits. In this way the average common mode output DC voltage can be set to particular voltage levels.

摘要翻译： 公开了一种适用于全差分运算放大器电路中的全差分电流反馈放大器。 对称低输入阻抗输入电路接收差分输入电流，并提供一组对应于差分输入电流的四个电流。 这些电流被输入到一对减法电路，该对减法电路响应于正差异而输出第一电压信号，第二电压信号响应于负差值。 在一些实施例中，这些信号可以被进一步放大。 提供了一种共模电路，其对输出电压进行平均并响应减法电路反馈电流。 以这种方式，平均共模输出直流电压可以设置为特定的电压电平。

公开(公告)号：US20050275466A1

公开(公告)日：2005-12-15

申请号：US10864950

申请日：2004-06-10

申请人： Uday Dasgupta ,  Chun Tan

发明人： Uday Dasgupta ,  Chun Tan

IPC分类号： H03F3/08

CPC分类号： H03F3/08

摘要： A Gigabit/s transimpedance amplifier system includes a forward-path amplifier section with a very large bandwidth and an overall frequency-selective feedback section which is active only from DC to low frequencies. The forward-path of the amplifier comprises a regulated cascode for receiving the input signal, a regulated cascode for receiving the feedback signal, a single-ended to differential converter and an output buffer. Stability and frequency selection is achieved by a bandwidth-limited operational amplifier in the feedback path. The Miller multiplication of a capacitive means in the operational amplifier creates a low-frequency pole and stabilizes the feedback loop and thereby limits the frequency range of the feedback.

摘要翻译： 千兆/秒跨阻放大器系统包括具有非常大带宽的前向路径放大器部分和仅从DC到低频有效的总频率选择反馈部分。 放大器的前向路径包括用于接收输入信号的调节共源共栅，用于接收反馈信号的调节共源共栅，单端到差分转换器和输出缓冲器。 稳定性和频率选择由反馈路径中的带宽限制运算放大器实现。 运算放大器中的电容装置的米勒乘法器产生低频极点并稳定反馈回路，从而限制反馈的频率范围。

公开(公告)号：US06839399B2

公开(公告)日：2005-01-04

申请号：US10403446

申请日：2003-03-31

申请人： Chun Geik Tan ,  Uday Dasgupta

发明人： Chun Geik Tan ,  Uday Dasgupta

IPC分类号： H03K23/66 ,  H03K23/68 ,  H03K21/02

CPC分类号： H03K23/68 ,  H03K23/662

摘要： This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.

公开(公告)号：US06566961B2

公开(公告)日：2003-05-20

申请号：US09821511

申请日：2001-03-30

申请人： Uday Dasgupta ,  Teo Tian Hwee

发明人： Uday Dasgupta ,  Teo Tian Hwee

IPC分类号： H03F304

CPC分类号： H03F3/45183 ,  H03F2203/45508 ,  H03F2203/45544 ,  H03F2203/45562 ,  H03F2203/45631 ,  H03F2203/45702

摘要： A wide-band single-ended to differential converter (DC to 1 GHz) with very low amplitude and phase matching errors, of the order of 0.01 dB and 0.15 degrees respectively and using CMOS technology, is comprised of a first and a second stage. The very low amplitude and phase matching errors have been achieved firstly by the use of capacitive means CD across the gate and source of the first stage MOS transistor M1 with a value equal to the drain to ground (reference potential) parasitic capacitance of the tail current source device for the first stage, and secondly by using equal valued capacitive means CF1, CF2 in the second stage and setting their values to be several (5-10) times more than the gate-drain parasitic capacitances of either of the differential transistors of the second stage.

公开(公告)号：US06437612B1

公开(公告)日：2002-08-20

申请号：US09996287

申请日：2001-11-28

申请人： Uday Dasgupta ,  Wooi Gan Teoh

发明人： Uday Dasgupta ,  Wooi Gan Teoh

IPC分类号： H03B100

CPC分类号： H03F1/308 ,  H03F1/301 ,  H03F2200/162

摘要： A buffer amplifier comprising a source follower-common drain circuit with a feedback path from the output of the drain follower to the input gate of the source follower. The feedback circuit is designed such that the output of the drain follower can be guaranteed to be at a voltage midway between the positive and the negative voltage supply of the circuit. This is the optimum operating point since it allows the largest signal swing. A small transconductance is realized by biasing the transistors of the feedback amplifier with very low currents; preferably by operating them in their weak inversion region. Feedback through the feedback amplifier is only present at DC (direct current) and at very low frequencies. This stabilizes the DC voltage at the drain of the common drain transistor, which, via an output capacitor, is also the output of the buffer amplifier.

摘要翻译： 一种缓冲放大器，包括源极跟随器 - 公共漏极电路，其具有从漏极跟随器的输出端到源极跟随器的输入栅极的反馈路径。 反馈电路被设计成使得能够保证漏极跟随器的输出处于电路的正电压和负电源之间的中间电压。 这是最佳的操作点，因为它允许最大的信号摆幅。 通过以非常低的电流偏置反馈放大器的晶体管来实现小跨导; 优选通过将它们操作在它们的弱反转区域中。 通过反馈放大器的反馈仅存在于DC（直流）和非常低的频率下。 这使得公共漏极晶体管的漏极处的直流电压稳定，其通过输出电容器也是缓冲放大器的输出。

公开(公告)号：US20100066449A1

公开(公告)日：2010-03-18

申请号：US12486759

申请日：2009-06-18

申请人： Uday Dasgupta

发明人： Uday Dasgupta

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F1/086 ,  H03F2200/153 ,  H03F2200/45 ,  H03F2203/45632 ,  H03F2203/45674

摘要： A three-stage frequency-compensated operational amplifier includes a first-stage circuit, a second-stage circuit incorporated with a first compensation circuit, a third-stage circuit, and a second compensation circuit. The three-stage frequency-compensated operational amplifier functions as a two-stage operational amplifier at high frequencies, thereby capable of driving large capacitive loads with low power consumption.

摘要翻译： 三级频率补偿运算放大器包括第一级电路，并入有第一补偿电路的第二级电路，第三级电路和第二补偿电路。 三级频率补偿运算放大器在高频下用作两级运算放大器，从而能够以低功耗驱动大容量负载。